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R32C/120 Group Datasheet
PRELIMINARY
R32C/120 Group
RENESAS MCU
REJ03B0236-0050 Rev.0.50 Jul 31, 2008
1.
1.1
Overview
Features
The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral functions, provides support for a vast range of application fields. The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture, multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of onchip peripheral devices -- UART, CRC, DMAC, A/D and D/A converters, timers, I2C, and WDT enables to minimize external components. The R32C/100 Series, in particular, provides the R32C/120 Group, a product specific to vehicle network. This product, provided as 100-pin plastic molded LQFP package, configures one channel of CAN, two channels of LIN, and standard peripherals.
1.1.1
Applications
Automotive, audio, communication equipment, industrial equipment etc.
Notes to users:
* While the information contained herein is believed to be accurate, it may contain technical inaccuracies or typographical errors. * Specifications may be subject to change due to product improvements or other reasons. Please verify the document is the latest version available.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 1 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
1.1.2
Performance Overview
Table 1.1 and Table 1.2 show the performance overview of the R32C/120 Group. Table 1.1 Unit CPU R32C/120 Group Performance (1/2) Function Performance Central processing R32C/100 Series CPU Core unit * Basic instructions: 108 * Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz) * Multiplier: 32-bit x 32-bit 64-bit * Multiply-accumulate unit: 32-bit x 32-bit + 64-bit 64-bit * IEEE-754 floating point standard: Single precision * 32-bit barrel shifter * Operating mode: Single-chip mode Flash memory: 128/256 Kbytes RAM: 12/20 Kbytes Data flash: 4 Kbytes x 2 blocks E2dataFlash: none (1)/4 Kbytes Refer to Table 1.3 for details Low voltage detector Clock generator Optional (2) Low voltage detection interrupt * 4 circuits (main clock, sub clock, PLL, on-chip oscillator) * Oscillation stop detector: Main clock oscillator stop/re-oscillation detection * Frequency divide circuit: Divide-by-2 to divide-by-24 selectable * Low power modes: Wait mode, stop mode Interrupt vectors: 261 External interrupt inputs: NMI, INT x 6, key input x 4 Interrupt priority levels: 7 levels 15 bits x 1 (selectable input frequency from prescaler output) Automatic timer start function is available 4 channels * Cycle-steal transfer mode * Request sources: 44 * 2 transfer modes: Single transfer, repeat transfer * Can be activated by any peripheral interrupt source * 3 transfer functions: Immediate data transfer, calculation transfer, chained transfer * 2 input-only ports * 84 CMOS inputs/outputs * A pull-up resistor is selectable for every 4 input ports
Memory
Voltage Detector Clock
Interrupts
Watchdog Timer DMA DMAC
DMAC II
I/O Ports
Programmable I/O ports
Notes: 1. Please contact a Renesas sales office to use the non-E2dataFlash version. 2. Please contact a Renesas sales office to use the optional feature.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 2 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
Table 1.2 Unit Timer
R32C/120 Group Performance (2/2) Function Timer A Performance 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Two-phase pulse signal processing in event counter mode (twophase encoder input) x 3 16-bit timer x 6 Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode
Timer B
Three-phase motor Three-phase motor control timer x1 (timers A1, A2, A4, and B2 used) control timer 8-bit programmable dead time timer Serial Interface A/D Converter UART0 to UART4 Asynchronous/synchronous serial interface x 5 channels * I2C-bus (UART0 to UART2) * Special mode 2 (UART0 to UART2) 10-bit resolution x 26 channels Sample & hold functionality integrated Self Test/Open-Circuit Detection Assist 8-bit resolution x 2 CRC-CCITT (X16 + X12 + X5 + 1) 16 bits x 16 bits Time measurement (input capture): 16 bits x 16 Digital debounce circuit contained Waveform generation (output compare): 16 bits x 16 Phase shift waveform output mode contained 1 channel * Synchronous serial communication mode * 4-wire serial bus mode Programmable character length: 8 to 16 bits 2 channels 1 channel CAN functionality compliant with ISO11898-1 32 mailboxes Programming and erasure supply voltage: VCC = 3.0 to 5.5 V Minimum endurance: 1, 000 erase/program cycles Read protection: ROM code protect, ID code check Debugging: On-chip debug, on-board flash reprogramming Minimum endurance: 100, 000 erase/program cycles 64 MHz/VCC = 3.0 to 5.5 V -40C to 85C (version J) -40C to 105C (version L) (1) -40C to 125C (version K) 36 mA (VCC = 5.0 V, f(CPU) = 64 MHz) 8 A (VCC = 3.3 V, f(XCIN) = 32.768 kHz, wait mode) 100-pin plastic molded LQFP (PLQP0100KB-A)
D/A Converter CRC Calculator X-Y Converter Intelligent I/O
Serial Bus Interface
LIN Module CAN Module
Flash Memory
E2dataFlash Operating Frequency/Supply Voltage Operating Temperature
Current Consumption Package
Note: 1. Please contact a Renesas sales office to use the version L products.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 3 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
1.2
Product Information
Table 1.3 lists the product information and Figure 1.1 shows the details of the part number. Table 1.3 R32C/120 Group Product List Package Code (1) ROM Capacity (2) RAM Capacity (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) (D) 256 Kbytes + 8 Kbytes 20 Kbytes NA
(3)
As of July, 2008 E2dataFlash 4 Kbytes 128 Kbytes + 8 Kbytes 12 Kbytes NA (3) Remarks Version J Version L (3) Version K Version J Version L (3) Version K Version J 4 Kbytes Version L (3) Version K Version J Version L (3) Version K
Part Number R5F64200JFB R5F64200LFB R5F64200KFB R5F6420EJFB R5F6420ELFB R5F6420EKFB R5F64201JFB R5F64201LFB R5F64201KFB R5F6420FJFB R5F6420FLFB R5F6420FKFB
PLQP0100KB-A
(D): Under development Notes: 1. The old package code is as follows: PLQP0100KB-A: 100P6Q-A 2. Data flash memory provides an additional 8 Kbytes of ROM capacity. 3. Please contact a Renesas sales office to use the non-E2dataFlash version or the version L products.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 4 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
Part Number
R5 F 64 20 1 J -XXX FB
Package Code FB : PLQP0100KB-A ROM Number Omitted in the flash memory version Temperature Code J : -40C to 85C L : -40C to 105C K : -40C to 125C ROM/RAM/E2dataFlash Capacity 0 : 128 KB / 12 KB / 4 KB 1 : 256 KB / 20 KB / 4 KB E : 128 KB / 12 KB / none F : 256 KB / 20 KB / none R32C/120 Group R32C/100 Series Memory Type F : Flash memory version
Figure 1.1
Part Numbering
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 5 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows a block diagram of the R32C/120 Group.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6 Port P7
Peripheral functions Timer:
Timer A Timer B 16 bits x 5 timers 16 bits x 6 timers
8
A/D converter:
10 bits x 1 circuit 26 inputs
Clock generator:
4 circuits - XIN-XOUT - XCIN-XCOUT - On-chip oscillator - PLL frequency synthesizer
Port P8
Three-phase motor controller Serial interface:
5 channels
D/A converter:
8 bits x 2 channels
7
X-Y converter:
16 bits x 16 bits
Watchdog timer:
15 bits P8_5
Serial bus interface:
1 channel
DMAC CRC calculator (CCITT)
X16 + X12 + X5 + 1
CAN Module:
1 channel
DMAC II Memory ROM
P9_1
R32C/100 Series CPU Core
R2R0 R2R0 R3R1 R3R1 R6R4 R6R4 R7R5 R7R5 A0 A0 A1 A1 A2 A2 A3 A3 FB FB SB SB FLG INTB ISP USP PC SVF SVP VCT
LIN Module:
2 channels
Port P9
RAM Multiplier
Intelligent I/O
Time measurement: 16 Wave generation: 16
5
Port P10
E2dataFlash
Floating-point unit
8
Figure 1.2
R32C/120 Group Block Diagram
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 6 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
1.4
Pin Assignment
Figure 1.3 shows the pin assignment (top view) and Table 1.4 to Table 1.6 show the pin characteristics.
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
IIO0_2 / IIO1_2 / SSI0 / P1_2 IIO0_1 / IIO1_1 / SSCK0 / P1_1 IIO0_0 / IIO1_0 / SSO0 / P1_0 AN0_7 / P0_7 AN0_6 / P0_6 AN0_5 / P0_5 AN0_4 / P0_4 AN0_3 / P0_3 AN0_2 / P0_2 AN0_1 / P0_1 AN0_0 / P0_0 KI3 / AN_7 / P10_7 KI2 / AN_6 / P10_6 KI1 / AN_5 / P10_5 KI0 / AN_4 / P10_4 AN_3 / P10_3 AN_2 / P10_2 AN_1 / P10_1 AVSS AN_0 / P10_0 VREF AVCC / VCC RXD4 / TB2IN / ADTRG / P9_7 TXD4 / ANEX1 / P9_6 CLK4 / ANEX0 / P9_5
51
P1_3 / SCS0 / IIO0_3 / IIO1_3 P1_4 / TB0IN / IIO0_4 / IIO1_4 P1_5 / INT3 / IIO0_5 / IIO1_5 P1_6 / INT4 / IIO0_6 / IIO1_6 P1_7 / INT5 / IIO0_7 / IIO1_7 P2_0 / AN2_0 P2_1 / AN2_1 P2_2 / AN2_2 P2_3 / AN2_3 P2_4 / AN2_4 P2_5 / AN2_5 P2_6 / AN2_6 P2_7 / AN2_7 VSS P3_0 / TA0OUT / LIN0OUT / UD0A / UD1A VCC P3_1 / TA3OUT / LIN0IN / UD0B / UD1B P3_2 / TA1OUT / V / LIN1OUT P3_3 / TA1IN / V / LIN1IN P3_4 / TA2OUT / W / CLK4 P3_5 / TA2IN / W / RXD4 P3_6 / TA4OUT / U / TXD4 P3_7 / TA4IN / U / TB1IN / CTS4 / RTS4 P4_0 / CTS3 / RTS3 / IIO1_0 P4_1 / CLK3 / IIO1_1
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43
R32C/120 GROUP
PLQP0100KB-A (100P6Q-A) (Top view)
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
P4_2 / RXD3 / IIO1_2 P4_3 / TXD3 / IIO1_3 P4_4 / LIN0OUT / IIO1_4 P4_5 / LIN0IN / IIO1_5 P4_6 / LIN1OUT / IIO1_6 P4_7 / LIN1IN / IIO1_7 P5_0 / IIO0_0 P5_1 / IIO0_1 P5_2 / IIO0_2 P5_3 / CLKOUT / IIO0_3 P5_4 / IIO0_4 P5_5 / IIO0_5 P5_6 / IIO0_6 P5_7 / IIO0_7 P6_0 / TB0IN / CTS0 / RTS0 / SS0 / SCS0 P6_1 / TB1IN / CLK0 / SSCK0 P6_2 / TB2IN / RXD0 / SCL0 / STXD0 / SSI0 P6_3 / TB5IN / TXD0 / SDA0 / SRXD0 / SSO0 P6_4 / CTS1 / RTS1 / SS1 P6_5 / CLK1 P6_6 / RXD1 / SCL1 / STXD1 P6_7 / TXD1 / SDA1 / SRXD1 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2 / IIO1_7 P7_2 / TA1OUT / V / CLK2
(Note 1)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note: 1. The position of pin number 1 varies by product. Refer to the index mark in attached "Package Dimensions".
Figure 1.3
Pin Assignment (top view)
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 7 of 96
RTS4 / CTS4 / TB4IN / DA1 / P9_4 TB3IN / DA0 / P9_3 VDC0 P9_1 VDC1 NSD CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC NMI / P8_5 INT2 / P8_4 CAN0WU / CAN0IN / INT1 / P8_3 CAN0OUT / INT0 / P8_2 UD0B / UD1B / IIO1_5 / LIN1OUT / RTS3 / CTS3 / TA3OUT / U / TA4IN / P8_1 UD0A / UD1A / LIN1IN / RXD3 / U / TA4OUT / P8_0 UD0B / UD1B / IIO1_4 / CAN0WU / CAN0IN / CLK3 / TA3IN / P7_7 UD0A / UD1A / IIO1_3 / CAN0OUT / TXD3 / TA3OUT / P7_6 IIO1_2 / LIN0IN / W / TA2IN / P7_5 IIO1_1 / LIN0OUT / W / TA2OUT / P7_4 IIO1_0 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
25
1
2
3
4
5
6
7
8
9
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
Table 1.4
Pin Control No. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VDC1 NSD CNVSS XCIN RESET XOUT VSS XIN VCC VDC0
Pin Characteristics (1/3)
Port P9_4 P9_3 P9_1 Interrupt Pin Timer Pin TB4IN TB3IN UART Pin CTS4/RTS4 Intelligent I/O Pin LIN / CAN Module Pin Analog Pin DA1 DA0
P8_7
XCOUT P8_6
P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2
NMI INT2 INT1 INT0 TA4IN/U/ TA3OUT TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TB5IN/ TA0IN TA0OUT CTS2/RTS2/SS2 TA1OUT/V CLK2 RXD2/SCL2/STXD2 IIO1_7 TXD2/SDA2/SRXD2 IIO1_6 TXD1/SDA1/SRXD1 RXD1/SCL1/STXD1 CLK1 CTS1/RTS1/SS1 TB5IN TB2IN TXD0/SDA0/ SRXD0/SSO0 RXD0/SCL0/STXD0/ SSI0 CTS3/RTS3 CAN0IN/CAN0WU CAN0OUT IIO1_5/UD0B/UD1B LIN1OUT UD0A/UD1A LIN1IN
TA4OUT/U RXD3 CLK3 TXD3
IIO1_4/UD0B/UD1B CAN0IN/CAN0WU IIO1_3/UD0A/UD1A CAN0OUT IIO1_2 IIO1_1 IIO1_0 LIN0IN LIN0OUT
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 8 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
Table 1.5
Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 VSS VCC Control Pin
Pin Characteristics (2/3)
Port P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 Interrupt Pin Timer Pin TB1IN TB0IN UART Pin CLK0/SSCK0 CTS0/RTS0/SS0 IIO0_7 IIO0_6 IIO0_5 IIO0_4 IIO0_3 IIO0_2 IIO0_1 IIO0_0 IIO1_7 IIO1_6 IIO1_5 IIO1_4 TXD3 RXD3 CLK3 CTS3/RTS3 TA4IN/U/ TB1IN TA2IN/W TA1IN/V TA1OUT/V TA3OUT TA0OUT UD0B/UD1B UD0A/UD1A CTS4/RTS4 IIO1_3 IIO1_2 IIO1_1 IIO1_0 LIN1IN LIN1OUT LIN0IN LIN0OUT Intelligent I/O Pin LIN / CAN Module Pin Analog Pin
CLKOUT P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 INT5 INT4 INT3 TB0IN
TA4OUT/U TXD4 RXD4 LIN1IN LIN1OUT LIN0IN LIN0OUT AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 IIO0_7/IIO1_7 IIO0_6/IIO1_6 IIO0_5/IIO1_5 IIO0_4/IIO1_4 TA2OUT/W CLK4
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 9 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
Table 1.6
Pin Control No. Pin 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VREF AVCC/ VCC AVSS
Pin Characteristics (3/3)
Port P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 KI3 P10_6 KI2 P10_5 KI1 P10_4 KI0 P10_3 P10_2 P10_1 P10_0 Interrupt Pin Timer Pin UART Pin SCS0 SSI0 SSCK0 SSO0 Intelligent I/O Pin IIO0_3/IIO1_3 IIO0_2/IIO1_2 IIO0_1/IIO1_1 IIO0_0/IIO1_0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 LIN / CAN Module Pin Analog Pin
P9_7 P9_6 P9_5
TB2IN
RXD4 TXD4 CLK4
ADTRG ANEX1 ANEX0
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 10 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
1.5
Pin Definitions and Functions
Table 1.7 to Table 1.9 shows the pin definitions and functions.
Table 1.7 Pin Definitions and Functions (1/3)
Function Power supply Connecting pins for decoupling capacitor Analog power supply Reset input CNVSS Debug port Main clock input
Symbol VCC, VSS VDC0, VDC1
I/O I --
Description Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V A decoupling capacitor for internal voltage should be connected between VDC0 and VDC1 Power supply for the A/D converter. AVSS should be connected to VSS The MCU is reset when this pin is driven low This pin should be connected to VSS via a resistor. This pin is to communicate with a debugger. It should be connected to VCC via a resistor of 1 to 4.7 k Input/output for the main clock oscillator. A ceramic resonator or a crystal oscillator should be connected between pins XIN and XOUT. An external clock should be input at the XIN while leaving the XOUT open Input/output for the sub clock oscillator. A crystal oscillator should be connected between pins XCIN and XCOUT. An external clock should be input at the XCIN while leaving the XCOUT open Output of the clock with the same frequency as fC, f8, or f32 Input for external interrupts Input for NMI Input for the key input interrupt I/O ports in CMOS. Each port can be programmed to input or output under the control of the direction register. Pull-up resistors are selected for following 4-pin units, but are enabled only for the input pins: Pi_0 to Pi_3 and Pi_4 to Pi_7 (i = 0 to 10)
AVCC, AVSS
RESET
I I I I/O I O
CNVSS NSD XIN
Main clock output XOUT
Sub clock input Sub clock output Clock output
XCIN XCOUT CLKOUT
I O O I I I
External interrupt INT0 to INT5 input NMI input I/O ports P8_5/NMI P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4, P8_6, P8_7 P9_3 to P9_7 P10_0 to P10_7 P9_1 Key input interrupt KI0 to KI3
I/O
Input port
I
Input port in CMOS. Pull-up resistors are selected for P9_1 and P9_3
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 11 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
Table 1.8
Pin Definitions and Functions (2/3)
Function Timer A Timer B Three-phase motor control timer output Serial interface
Symbol TA0OUT to TA4OUT TA0IN to TA4IN TB0IN to TB5IN U, U, V, V, W, W
I/O I/O I I O
Description Timers A0 to A4 input/output Timers A0 to A4 input Timers B0 to B5 input Three-phase motor control timer output
CTS0 to CTS4 RTS0 to RTS4
I O I/O I O I/O I/O O I I I I I/O I O I
Handshake input Handshake output Transmit/receive clock input/output Serial data input Serial data output Serial data input/output Transmit/receive clock input/output Serial data output in slave mode Serial data input in slave mode Input to control serial interface special functions Analog input for the A/D converter
CLK0 to CLK4 RXD0 to RXD4 TXD0 to TXD4 I2C bus (simplified) Serial interface special functions A/D converter SDA0 to SDA2 SCL0 to SCL2 STXD0 to STXD2 SRXD0 to SRXD2
SS0 to SS2
AN_0 to AN_7 AN0_0 to AN0_7 AN2_0 to AN2_7
ADTRG
External trigger input for the A/D converter Expanded analog input for the A/D converter and output in external op-amp connection mode Expanded analog input for the A/D converter Output for the D/A converter Reference voltage input for the A/D converter and D/ A converter
ANEX0 ANEX1 D/A converter DA0 to DA1 Reference voltage VREF input
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 12 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
1. Overview
Table 1.9
Pin Definitions and Functions (3/3)
Function Intelligent I/O
Symbol IIO0_0 to IIO0_7 IIO1_0 to IIO1_7 UD0A, UD0B, UD1A, UD1B
I/O I/O I/O I I/O I/O I/O I/O O I I O I
Description Input/output for the Intelligent I/O group 0. Either input capture or output compare is selectable Input/output for the Intelligent I/O group 1. Either input capture or output compare is selectable Input for the two-phase encoder Serial data output. Functions as serial data input/ output in 4-wire serial bus mode Serial data input. Functions as serial data input/ output in 4-wire serial bus mode Transmit/receive clock input/output Input/output to control the synchronous serial interface Transmit data output for the LIN communications Receive data input for the LIN communications Receive data input for the CAN communications Transmit data output for the CAN communications Input for the CAN wake-up interrupt
Serial bus interface
SSO0 SSI0 SSCK0
SCS0
LIN module CAN module
LIN0OUT to LIN1OUT LIN0IN to LIN1IN CAN0IN CAN0OUT
CAN0WU
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 13 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Ten specific of these registers (R2R0, R3R1, R6R4, R7R5, A0, A1, A2, A3, SB, and FB) configure two sets of register banks.
General purpose registers
b31
b23
b15
b7
b0
R2R0 R3R1 R6R4 R7R5
R2H R3H R6 R7
R2L R3L
R0H R1H R4 R5 A0 A1 A2 A3 SB FB USP ISP
R0L R1L Data registers (1)
Address registers (1)
Static base register (1) Frame base register (1) User stack pointer Interrupt stack pointer Interrupt vector table base register Program counter Flag register
INTB PC FLG
b31
b24 b23
b16 b15
b8 b7
b0
RND DP
IPL FU FO
U I OBSZDC
All blank fields are reserved.
Fast interrupt registers
b31
b0
SVF SVP VCT
Save flag register Save PC register Vector register
b0
DMAC-associated registers (2)
b31
b23
DMD0 DMD0 DMD0 DMD0 DCT0 DCT0 DCT0 DCT0 DCR0 DCR0 DCR0 DCR0 DSA0 DSA0 DSA0 DSA0 DSR0 DSR0 DSR0 DSR0 DDA0 DDA0 DDA0 DDA0 DDR0 DDR0 DDR0 DDR0
DMA mode register DMA terminal count register DMA terminal count reload register DMA source address register DMA source address reload register DMA destination address register DMA destination address reload register
Notes: 1. There are two banks of these registers. 2. There are four identical sets of DMAC-associated registers.
Figure 2.1
CPU Registers
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 14 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
2. Central Processing Unit (CPU)
2.1 2.1.1
General Purpose Registers Data Registers (R2R0, R3R1, R6R4, and R7R5)
These 32-bit registers are primarily used for transfers and arithmetic/logic operations. Each of the registers can be divided into the upper and the lower 16-bit registers, e.g. R2R0 can be divided into R2 and R0, R3R0 can be divided into R3 and R1, etc. Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: the upper (R2h, and R3H), the mid-upper (R2L, and R3L), the mid-lower (R0H, and R1H), and the lower (R0L, and R1L).
2.1.2
Address Registers (A0, A1, A2, and A3)
These 32-bit registers have the similar functions to the data registers. They are also used for address register indirect addressing and address register relative addressing.
2.1.3
Static Base Register (SB)
This 32-bit register is used for SB relative addressing.
2.1.4
Frame Base Register (FB)
This 32-bit register is used for FB relative addressing.
2.1.5
Program Counter (PC)
This 32-bit counter indicates the address of the instruction to be executed next.
2.1.6
Interrupt Vector Table Base Register (INTB)
This 32-bit register indicates the start address of a relocatable vector table.
2.1.7
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack pointer (ISP). They are switched by the U flag. Refer to 2.1.8 "Flag Register (FLG)" for details on the U flag. The stack pointer (USP/ISP) to be used can be switched by the stack pointer select flag (U flag). This flag is bit 7 in the flag register (FLG). A multiple of 4 should be set to USP or ISP, which enables faster interrupt sequence due to less memory access.
2.1.8
Flag Register (FLG)
This 32-bit register indicates the CPU status.
2.1.8.1
Carry Flag (C flag)
This flag has the carry, borrow, shifted-out bit, etc. generated in the arithmetic logic unit (ALU).
2.1.8.2
Debug Flag (D flag)
This flag is used exclusively for debugging. Only set this bit to 0.
2.1.8.3
Zero Flag (Z flag)
This flag becomes 1 when an operation results in 0; in all other cases, this flag becomes 0.
2.1.8.4
Sign Flag (S flag)
This flag becomes 1 when an operation results in a negative; in all other cases, this flag becomes 0. REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 15 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
2. Central Processing Unit (CPU)
2.1.8.5
Register Bank Select Flag (B flag)
This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the register bank 1 is selected.
2.1.8.6
Overflow Flag (O flag)
This flag becomes 1 if an operation results in an overflow; in all other cases, this flag becomes 0.
2.1.8.7
Interrupt Enable Flag (I flag)
This flag enables a maskable interrupt. It indicates 0 when an interrupt is disabled, and 1 when an interrupt is enabled. Once an interrupt is accepted, the flag is set to 0.
2.1.8.8
Stack Pointer Select Flag (U flag)
This flag indicates 0 when the interrupt stack pointer (ISP) is selected, and 1 when the user stack pointer (USP) is selected. It is set to 0 when a hardware interrupt is accepted or the INT instruction whose software interrupt number is 0 to 127 is executed.
2.1.8.9
Floating-point Underflow Flag (FU flag)
This flag becomes 1 if a floating point operation results in an underflow; in all other cases, this flag becomes 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.10
Floating-point Overflow Flag (FO flag)
This flag becomes 1 if a floating point operation results in an overflow; in all other cases, this flag becomes 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.11
Processor Interrupt Priority Level (IPL)
The 3-bit processor interrupt priority level (IPL) specifies eight processor interrupt priority levels from 0 to 7. If a requested interrupt's priority level is higher than the processor interrupt priority level (IPL), this interrupt is enabled. If the processor interrupt priority level (IPL) is set to 111b (level 7), any interrupt is disabled.
2.1.8.12
Fixed-point Designation Bit (DP bit)
This bit designates a fixed point. It also designates which part of the multiplication result should be taken. It is used for MULX instruction.
2.1.8.13
Floating-point Rounding Mode (RND)
The 2-bit floating point rounding mode designates a rounding mode for the operation result.
2.1.8.14
Reserved
The fields are written with 0. The read value is undefined.
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
2. Central Processing Unit (CPU)
2.2
Fast Interrupt Registers
These registers are exclusively used to achieve high performance of interrupt sequence. Three types of register are shown as below.
2.2.1
Save Flag Register (SVF)
This 32-bit register is used to save the flag register when a fast interrupt is generated.
2.2.2
Save PC Register (SVP)
This 32-bit register is used to save the program counter when a fast interrupt is generated.
2.2.3
Vector Register (VCT)
This 32-bit register is used to indicate a jump address when a fast interrupt is generated.
2.3
DMAC-associated Registers
Seven types of register are shown as below.
2.3.1
DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)
These 32-bit registers are used to set DMA transfer mode, bit rate etc.
2.3.2
DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)
These 24-bit registers are used to set DMA transfer counting.
2.3.3
DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)
These 24-bit registers are used to set the reloaded value for DMA terminal count register.
2.3.4
DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)
These 32-bit registers are used to set DMA source address.
2.3.5
DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)
These 32-bit registers are used to set the reloaded value for DMA source address register.
2.3.6
DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)
These 32-bit registers are used to set DMA destination address.
2.3.7
DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and DDR3)
These 32-bit registers are used to set the reloaded value for DMA destination address register.
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
3. Memory
3.
Memory
Figure 3.1 shows a memory mapping of the R32C/120 Group. The R32C/120 Group provides 4-Gbyte address space from 00000000h to FFFFFFFFh. The internal ROM is allocated from address FFFFFFFFh down. For example, a 256-Kbyte internal ROM is addressed from FFFC0000h to FFFFFFFFh. The fixed interrupt vectors are allocated from address FFFFFFDCh to FFFFFFFFh in which the starting address of each interrupt handler is stored. The internal RAM is allocated from address 00000400h up. For example, a 20-Kbyte internal RAM is addressed from 00000400h to 000053FFh. Besides being used for data storage, the internal RAM functions as stack(s) for a subroutine and/or an interrupt handler. Special Function Registers (SFRs), consisting of control registers for peripheral functions, are allocated from address 00000000h to 000003FFh and from 00040000h to 0004FFFFh. Any blank spaces within the SFRs are reserved. No access is allowed.
00000000h 00000400h Internal RAM Capacity 12 Kbytes 20 Kbytes XXXXXXXXh 00003400h 00005400h 00040000h 00050000h 00060000h 00062000h XXXXXXXXh
SFR1 Internal RAM
Reserved SFR2 Reserved Internal ROM (Data space) (1) FFFFFFDCh Undefined instruction Overflow BRK instruction Reserved Reserved Watchdog timer (2) Reserved NMI Reset FFFFFFFFh
Internal ROM Capacity 128 Kbytes 256 Kbytes YYYYYYYYh FFFE0000h FFFC0000h
Reserved
YYYYYYYYh Internal ROM FFFFFFFFh
Notes: 1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version. 2. The watchdog timer interrupt shares the vector table with the oscillation stop detection interrupt and lowvoltage detection interrupt.
Figure 3.1
Memory Mapping
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
4.
Special Function Registers (SFR)
SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List (1) to Table 4.41 SFR List (41) list the SFR details.
Table 4.1 SFR List (1)
Symbol Reset Value
Address Register 000000h 000001h 000002h 000003h 000004h Clock Control Register 000005h 000006h Flash Memory Control Register 000007h Protect Release Register 000008h 000009h 00000Ah 00000Bh 00000Ch 00000Dh 00000Eh 00000Fh 000010h 000011h 000012h 000013h 000014h 000015h 000016h 000017h 000018h 000019h 00001Ah 00001Bh 00001Ch Flash Memory Rewrite Bus Control Register 00001Dh 00001Eh Peripheral Bus Control Register 00001Fh 000020h to 00005Fh X: Undefined Blanks are reserved. No access is allowed.
CCR FMCR PRR
18h 01h 00h
FEBC PBC
0000h 0504h
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.2
Address 000060h 000061h 000062h 000063h 000064h 000065h 000066h 000067h 000068h 000069h 00006Ah 00006Bh 00006Ch 00006Dh 00006Eh 00006Fh 000070h 000071h 000072h 000073h 000074h 000075h 000076h 000077h 000078h 000079h 00007Ah 00007Bh 00007Ch 00007Dh 00007Eh 00007Fh 000080h 000081h 000082h 000083h 000084h 000085h 000086h 000087h
SFR List (2)
Register Timer B5 Interrupt Control Register UART2 Receive/ACK Interrupt Control Register Symbol TB5IC S2RIC Reset Value XXXX X000b XXXX X000b
DMA0 Transfer Complete Interrupt Control Register UART0 Start/Stop Condition Detection Interrupt Control Register DMA2 Transfer Complete Interrupt Control Register A/D Converter 0 Convert Completion Interrupt Control Register Timer A0 Interrupt Control Register Intelligent I/O Interrupt Control Register 0 Timer A2 Interrupt Control Register Intelligent I/O Interrupt Control Register 2 Timer A4 Interrupt Control Register Intelligent I/O Interrupt Control Register 4 UART0 Receive/ACK Interrupt Control Register Intelligent I/O Interrupt Control Register 6 UART1 Receive/ACK Interrupt Control Register Intelligent I/O Interrupt Control Register 8 Timer B1 Interrupt Control Register Intelligent I/O Interrupt Control Register 10 Timer B3 Interrupt Control Register INT5 Interrupt Control Register CAN0 Wake-up Interrupt Control Register INT3 Interrupt Control Register INT1 Interrupt Control Register LIN Low Detection Interrupt Control Register UART2 Transmit/NACK Interrupt Control Register
DM0IC BCN0IC DM2IC AD0IC TA0IC IIO0IC TA2IC IIO2IC TA4IC IIO4IC S0RIC IIO6IC S1RIC IIO8IC TB1IC IIO10IC TB3IC INT5IC C0WIC INT3IC INT1IC LLDIC S2TIC
XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XX00 X000b XXXX X000b XXXX X000b
UART2 Start/Stop Condition Detection Interrupt Control Register X: Undefined Blanks are reserved. No access is allowed.
BCN2IC
XXXX X000b
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.3
SFR List (3)
Symbol DM1IC BCN1IC DM3IC KUPIC TA1IC IIO1IC TA3IC IIO3IC S0TIC IIO5IC S1TIC IIO7IC TB0IC IIO9IC TB2IC IIO11IC TB4IC INT4IC INT2IC INT0IC IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Reset Value XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XX00 X000b 0000 0XX1b 0000 0XX1b 0000 0X01b 0000 0XX1b 000X 0XX1b 0000 00X1b 0000 00X1b 000X 00X1b 0000 00X1b 0000 00X1b 0000 00X1b 0000 00X1b
Address Register 000088h DMA1 Transfer Complete Interrupt Control Register 000089h UART1 Start/Stop Condition Detection Interrupt Control Register 00008Ah DMA3 Transfer Complete Interrupt Control Register 00008Bh Key Input Interrupt Control Register 00008Ch Timer A1 Interrupt Control Register 00008Dh Intelligent I/O Interrupt Control Register 1 00008Eh Timer A3 Interrupt Control Register 00008Fh Intelligent I/O Interrupt Control Register 3 000090h UART0 Transmit/NACK Interrupt Control Register 000091h Intelligent I/O Interrupt Control Register 5 000092h UART1 Transmit/NACK Interrupt Control Register 000093h Intelligent I/O Interrupt Control Register 7 000094h Timer B0 Interrupt Control Register 000095h Intelligent I/O Interrupt Control Register 9 000096h Timer B2 Interrupt Control Register 000097h Intelligent I/O Interrupt Control Register 11 000098h Timer B4 Interrupt Control Register 000099h 00009Ah INT4 Interrupt Control Register 00009Bh 00009Ch INT2 Interrupt Control Register 00009Dh 00009Eh INT0 Interrupt Control Register 00009Fh 0000A0h Intelligent I/O Interrupt Request Register 0 0000A1h Intelligent I/O Interrupt Request Register 1 0000A2h Intelligent I/O Interrupt Request Register 2 0000A3h Intelligent I/O Interrupt Request Register 3 0000A4h Intelligent I/O Interrupt Request Register 4 0000A5h Intelligent I/O Interrupt Request Register 5 0000A6h Intelligent I/O Interrupt Request Register 6 0000A7h Intelligent I/O Interrupt Request Register 7 0000A8h Intelligent I/O Interrupt Request Register 8 0000A9h Intelligent I/O Interrupt Request Register 9 0000AAh Intelligent I/O Interrupt Request Register 10 0000ABh Intelligent I/O Interrupt Request Register 11 0000ACh 0000ADh 0000AEh 0000AFh X: Undefined Blanks are reserved. No access is allowed.
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.4
SFR List (4)
Symbol IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Address Register 0000B0h Intelligent I/O Interrupt Enable Register 0 0000B1h Intelligent I/O Interrupt Enable Register 1 0000B2h Intelligent I/O Interrupt Enable Register 2 0000B3h Intelligent I/O Interrupt Enable Register 3 0000B4h Intelligent I/O Interrupt Enable Register 4 0000B5h Intelligent I/O Interrupt Enable Register 5 0000B6h Intelligent I/O Interrupt Enable Register 6 0000B7h Intelligent I/O Interrupt Enable Register 7 0000B8h Intelligent I/O Interrupt Enable Register 8 0000B9h Intelligent I/O Interrupt Enable Register 9 0000BAh Intelligent I/O Interrupt Enable Register 10 0000BBh Intelligent I/O Interrupt Enable Register 11 0000BCh 0000BDh 0000BEh 0000BFh 0000C0h Serial Bus Interface 0 Interrupt Control Register 0000C1h CAN0 Transmit Interrupt Control Register 0000C2h 0000C3h CAN0 Error Interrupt Control Register 0000C4h 0000C5h 0000C6h 0000C7h 0000C8h 0000C9h 0000CAh 0000CBh 0000CCh 0000CDh 0000CEh 0000CFh 0000D0h CAN0 Transmit FIFO Interrupt Control Register 0000D1h 0000D2h 0000D3h 0000D4h 0000D5h LIN0 Interrupt Control Register 0000D6h 0000D7h 0000D8h E2dataFlash Interrupt Control Register 0000D9h 0000DAh 0000DBh 0000DCh 0000DDh UART3 Transmit Interrupt Control Register 0000DEh 0000DFh UART4 Transmit Interrupt Control Register X: Undefined Blanks are reserved. No access is allowed.
SS0IC C0TIC C0EIC
XXXX X000b XXXX X000b XXXX X000b
C0FTIC
XXXX X000b
L0IC
XXXX X000b
E2FIC
XXXX X000b
S3TIC S4TIC
XXXX X000b XXXX X000b
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.5
SFR List (5)
Symbol C0RIC Reset Value XXXX X000b
Address Register 0000E0h 0000E1h CAN0 Receive Interrupt Control Register 0000E2h 0000E3h 0000E4h 0000E5h 0000E6h 0000E7h 0000E8h 0000E9h 0000EAh 0000EBh 0000ECh 0000EDh 0000EEh 0000EFh 0000F0h CAN0 Receive FIFO Interrupt Control Register 0000F1h 0000F2h 0000F3h 0000F4h 0000F5h LIN1 Interrupt Control Register 0000F6h 0000F7h 0000F8h 0000F9h 0000FAh 0000FBh 0000FCh 0000FDh UART3 Receive Interrupt Control Register 0000FEh 0000FFh UART4 Receive Interrupt Control Register 000100h Group 1 Time Measurement/Waveform Generation Register 0 000101h 000102h Group 1 Time Measurement/Waveform Generation Register 1 000103h 000104h Group 1 Time Measurement/Waveform Generation Register 2 000105h 000106h Group 1 Time Measurement/Waveform Generation Register 3 000107h X: Undefined Blanks are reserved. No access is allowed.
C0FRIC
XXXX X000b
L1IC
XXXX X000b
S3RIC S4RIC G1TM0/G1PO0 G1TM1/G1PO1 G1TM2/G1PO2 G1TM3/G1PO3
XXXX X000b XXXX X000b XXXXh XXXXh XXXXh XXXXh
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.6
SFR List (6)
Symbol G1TM4/G1PO4 G1TM5/G1PO5 G1TM6/G1PO6 G1TM7/G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS Reset Value XXXXh XXXXh XXXXh XXXXh 0000 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 00h 00h 00h 00h 00h 00h 00h 00h XXXXh 00h 0000 0000b 00h 00h 00h 00h
Address Register 000108h Group 1 Time Measurement/Waveform Generation Register 4 000109h 00010Ah Group 1 Time Measurement/Waveform Generation Register 5 00010Bh 00010Ch Group 1 Time Measurement/Waveform Generation Register 6 00010Dh 00010Eh Group 1 Time Measurement/Waveform Generation Register 7 00010Fh 000110h Group 1 Waveform Generation Control Register 0 000111h Group 1 Waveform Generation Control Register 1 000112h Group 1 Waveform Generation Control Register 2 000113h Group 1 Waveform Generation Control Register 3 000114h Group 1 Waveform Generation Control Register 4 000115h Group 1 Waveform Generation Control Register 5 000116h Group 1 Waveform Generation Control Register 6 000117h Group 1 Waveform Generation Control Register 7 000118h Group 1 Time Measurement Control Register 0 000119h Group 1 Time Measurement Control Register 1 00011Ah Group 1 Time Measurement Control Register 2 00011Bh Group 1 Time Measurement Control Register 3 00011Ch Group 1 Time Measurement Control Register 4 00011Dh Group 1 Time Measurement Control Register 5 00011Eh Group 1 Time Measurement Control Register 6 00011Fh Group 1 Time Measurement Control Register 7 000120h Group 1 Base Timer Register 000121h 000122h Group 1 Base Timer Control Register 0 000123h Group 1 Base Timer Control Register 1 000124h Group 1 Timer Measurement Prescaler Register 6 000125h Group 1 Timer Measurement Prescaler Register 7 000126h Group 1 Function Enable Register 000127h Group 1 Function Select Register 000128h 000129h 00012Ah 00012Bh 00012Ch 00012Dh 00012Eh 00012Fh X: Undefined Blanks are reserved. No access is allowed.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 24 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.7
SFR List (7)
Symbol Reset Value
Address Register 000130h to 00016Fh 000170h 000171h 000172h 000173h 000174h 000175h 000176h 000177h 000178h 000179h 00017Ah 00017Bh 00017Ch 00017Dh 00017Eh 00017Fh 000180h Group 0 Time Measurement/Waveform Generation Register 0 000181h 000182h Group 0 Time Measurement/Waveform Generation Register 1 000183h 000184h Group 0 Time Measurement/Waveform Generation Register 2 000185h 000186h Group 0 Time Measurement/Waveform Generation Register 3 000187h 000188h Group 0 Time Measurement/Waveform Generation Register 4 000189h 00018Ah Group 0 Time Measurement/Waveform Generation Register 5 00018Bh 00018Ch Group 0 Time Measurement/Waveform Generation Register 6 00018Dh 00018Eh Group 0 Time Measurement/Waveform Generation Register 7 00018Fh 000190h Group 0 Waveform Generation Control Register 0 000191h Group 0 Waveform Generation Control Register 1 000192h Group 0 Waveform Generation Control Register 2 000193h Group 0 Waveform Generation Control Register 3 000194h Group 0 Waveform Generation Control Register 4 000195h Group 0 Waveform Generation Control Register 5 000196h Group 0 Waveform Generation Control Register 6 000197h Group 0 Waveform Generation Control Register 7 000198h Group 0 Time Measurement Control Register 0 000199h Group 0 Time Measurement Control Register 1 00019Ah Group 0 Time Measurement Control Register 2 00019Bh Group 0 Time Measurement Control Register 3 00019Ch Group 0 Time Measurement Control Register 4 00019Dh Group 0 Time Measurement Control Register 5 00019Eh Group 0 Time Measurement Control Register 6 00019Fh Group 0 Time Measurement Control Register 7 X: Undefined Blanks are reserved. No access is allowed.
G0TM0/G0PO0 G0TM1/G0PO1 G0TM2/G0PO2 G0TM3/G0PO3 G0TM4/G0PO4 G0TM5/G0PO5 G0TM6/G0PO6 G0TM7/G0PO7 G0POCR0 G0POCR1 G0POCR2 G0POCR3 G0POCR4 G0POCR5 G0POCR6 G0POCR7 G0TMCR0 G0TMCR1 G0TMCR2 G0TMCR3 G0TMCR4 G0TMCR5 G0TMCR6 G0TMCR7
XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0000 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 00h 00h 00h 00h 00h 00h 00h 00h
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 25 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.8
SFR List (8)
Symbol G0BT G0BCR0 G0BCR1 G0TPR6 G0TPR7 G0FE G0FS Reset Value XXXXh 00h 0000 0000b 00h 00h 00h 00h
Address Register 0001A0h Group 0 Base Timer Register 0001A1h 0001A2h Group 0 Base Timer Control Register 0 0001A3h Group 0 Base Timer Control Register 1 0001A4h Group 0 Timer Measurement Prescaler Register 6 0001A5h Group 0 Timer Measurement Prescaler Register 7 0001A6h Group 0 Function Enable Register 0001A7h Group 0 Function Select Register 0001A8h 0001A9h 0001AAh 0001ABh 0001ACh 0001ADh 0001AEh 0001AFh 0001B0h 0001B1h 0001B2h 0001B3h 0001B4h 0001B5h 0001B6h 0001B7h 0001B8h 0001B9h 0001BAh 0001BBh 0001BCh 0001BDh 0001BEh 0001BFh 0001C0h 0001C1h 0001C2h 0001C3h 0001C4h 0001C5h 0001C6h 0001C7h 0001C8h 0001C9h 0001CAh 0001CBh 0001CCh 0001CDh 0001CEh 0001CFh X: Undefined Blanks are reserved. No access is allowed.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 26 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.9
SFR List (9)
Symbol Reset Value
Address Register 0001D0h 0001D1h 0001D2h 0001D3h 0001D4h 0001D5h 0001D6h 0001D7h 0001D8h 0001D9h 0001DAh 0001DBh 0001DCh 0001DDh 0001DEh 0001DFh 0001E0h UART3 Transmit/Receive Mode Register 0001E1h UART3 Bit Rate Register 0001E2h UART3 Transmit Buffer Register 0001E3h 0001E4h UART3 Transmit/Receive Control Register 0 0001E5h UART3 Transmit/Receive Control Register 1 0001E6h UART3 Receive Buffer Register 0001E7h 0001E8h UART4 Transmit/Receive Mode Register 0001E9h UART4 Bit Rate Register 0001EAh UART4 Transmit Buffer Register 0001EBh 0001ECh UART4 Transmit/Receive Control Register 0 0001EDh UART4 Transmit/Receive Control Register 1 0001EEh UART4 Receive Buffer Register 0001EFh 0001F0h UART3, UART4 Transmit/Receive Control Register 2 0001F1h 0001F2h 0001F3h 0001F4h 0001F5h 0001F6h 0001F7h 0001F8h 0001F9h 0001FAh 0001FBh 0001FCh 0001FDh 0001FEh 0001FFh X: Undefined Blanks are reserved. No access is allowed.
U3MR U3BRG U3TB U3C0 U3C1 U3RB U4MR U4BRG U4TB U4C0 U4C1 U4RB U34CON
00h XXh XXXXh 00X0 1000b XXXX 0010b XXXX XXXXb XXXX 000Xb 00h XXh XXXXh 00X0 1000b XXXX 0010b XXXX XXXXb XXXX 000Xb X000 0000b
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.10
SFR List (10)
Symbol G0SDR G0PSCR G1SDR G1PSCR Reset Value 00h 00h 00h 00h
Address Register 000200h Group0 Phase Shift Waveform Output Mode Clock Division Setting Register 000201h Group0 Phase Shift Waveform Output Mode Control Register 000202h Group1 Phase Shift Waveform Output Mode Clock Division Setting Register 000203h Group1 Phase Shift Waveform Output Mode Control Register 000204h 000205h 000206h 000207h 000208h Timer B Event Clock Select Register 000209h 00020Ah 00020Bh 00020Ch 00020Dh 00020Eh 00020Fh 000210h IIO0_7 Digital Debounce Register 000211h IIO1_7 Digital Debounce Register 000212h 000213h 000214h 000215h 000216h 000217h 000218h 000219h 00021Ah 00021Bh 00021Ch 00021Dh 00021Eh 00021Fh 000220h Timer A1 Mirror Register 000221h 000222h Timer A1-1 Mirror Register 000223h 000224h Timer A2 Mirror Register 000225h 000226h Timer A2-1 Mirror Register 000227h 000228h Timer A4 Mirror Register 000229h 00022Ah Timer A4-1 Mirror Register 00022Bh 00022Ch 00022Dh 00022Eh 00022Fh X: Undefined Blanks are reserved. No access is allowed.
TBECKS
0000 0000b
IC07DDR IC17DDR
FFh FFh
TA1M TA11M TA2M TA21M TA4M TA41M
XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 28 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.11
SFR List (11)
Symbol Reset Value
Address Register 000230h to 0002BFh 0002C0h X0 Register Y0 Register 0002C1h 0002C2h X1 Register Y1 Register 0002C3h 0002C4h X2 Register Y2 Register 0002C5h 0002C6h X3 Register Y3 Register 0002C7h 0002C8h X4 Register Y4 Register 0002C9h 0002CAh X5 Register Y5 Register 0002CBh 0002CCh X6 Register Y6 Register 0002CDh 0002CEh X7 Register Y7 Register 0002CFh 0002D0h X8 Register Y8 Register 0002D1h 0002D2h X9 Register Y9 Register 0002D3h 0002D4h X10 Register Y10 Register 0002D5h 0002D6h X11 Register Y11 Register 0002D7h 0002D8h X12 Register Y12 Register 0002D9h 0002DAh X13 Register Y13 Register 0002DBh 0002DCh X14 Register Y14 Register 0002DDh 0002DEh X15 Register Y15 Register 0002DFh 0002E0h XY Control Register 0002E1h 0002E2h 0002E3h 0002E4h UART1 Special Mode Register 4 0002E5h UART1 Special Mode Register 3 0002E6h UART1 Special Mode Register 2 0002E7h UART1 Special Mode Register 0002E8h UART1 Transmit/Receive Mode Register 0002E9h UART1 Bit Rate Register 0002EAh UART1 Transmit Buffer Register 0002EBh 0002ECh UART1 Transmit/Receive Control Register 0 0002EDh UART1 Transmit/Receive Control Register 1 0002EEh UART1 Receive Buffer Register 0002EFh X: Undefined Blanks are reserved. No access is allowed.
X0R, Y0R X1R, Y1R X2R, Y2R X3R, Y3R X4R, Y4R X5R, Y5R X6R, Y6R X7R, Y7R X8R, Y8R X9R, Y9R X10R, Y10R X11R, Y11R X12R, Y12R X13R, Y13R X14R, Y14R X15R, Y15R XYC
XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXX XX00b
U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 29 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.12
SFR List (12)
Symbol Reset Value
Address Register 0002F0h 0002F1h 0002F2h 0002F3h 0002F4h 0002F5h 0002F6h 0002F7h 0002F8h 0002F9h 0002FAh 0002FBh 0002FCh 0002FDh 0002FEh 0002FFh 000300h Count Start Register for Timers B3, B4 and B5 000301h 000302h Timer A1-1 Register 000303h 000304h Timer A2-1 Register 000305h 000306h Timer A4-1 Register 000307h 000308h Three-phase PWM Control Register 0 000309h Three-phase PWM Control Register 1 00030Ah Three-phase Output Buffer Register 0 00030Bh Three-phase Output Buffer Register 1 00030Ch Dead Time Timer 00030Dh Timer B2 Interrupt Generating Frequency Set Counter 00030Eh 00030Fh 000310h Timer B3 Register 000311h 000312h Timer B4 Register 000313h 000314h Timer B5 Register 000315h 000316h 000317h 000318h 000319h 00031Ah 00031Bh Timer B3 Mode Register 00031Ch Timer B4 Mode Register 00031Dh Timer B5 Mode Register 00031Eh 00031Fh X: Undefined Blanks are reserved. No access is allowed.
TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
000X XXXXb XXXXh XXXXh XXXXh 00h 00h XX11 1111b XX11 1111b XXh XXh
TB3 TB4 TB5
XXXXh XXXXh XXXXh
TB3MR TB4MR TB5MR
00XX 0000b 00XX 0000b 00XX 0000b
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 30 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.13
SFR List (13)
Symbol Reset Value
Address Register 000320h 000321h 000322h 000323h 000324h 000325h 000326h 000327h 000328h 000329h 00032Ah 00032Bh 00032Ch 00032Dh 00032Eh 00032Fh 000330h 000331h 000332h 000333h 000334h UART2 Special Mode Register 4 000335h UART2 Special Mode Register 3 000336h UART2 Special Mode Register 2 000337h UART2 Special Mode Register 000338h UART2 Transmission/Receive Mode Register 000339h UART2 Bit Rate Register 00033Ah UART2 Transmit Buffer Register 00033Bh 00033Ch UART2 Transmit/Receive Control Register 0 00033Dh UART2 Transmit/Receive Control Register 1 00033Eh UART2 Receive Buffer Register 00033Fh 000340h Count Start Register 000341h Clock Prescaler Reset Register 000342h One-shot Start Register 000343h Trigger Select Register 000344h Increment/Decrement Counting Select Register 000345h 000346h Timer A0 Register 000347h 000348h Timer A1 Register 000349h 00034Ah Timer A2 Register 00034Bh 00034Ch Timer A3 Register 00034Dh 00034Eh Timer A4 Register 00034Fh X: Undefined Blanks are reserved. No access is allowed.
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 00h 0XXX XXXXb 00h 00h 0000 0000b XXXXh XXXXh XXXXh XXXXh XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 31 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.14
SFR List (14)
Symbol TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR Reset Value XXXXh XXXXh XXXXh 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 00XX 0000b 00XX 0000b 00XX 0000b XXXX XXX0b 0000 0000b
Address Register 000350h Timer B0 Register 000351h 000352h Timer B1 Register 000353h 000354h Timer B2 Register 000355h 000356h Timer A0 Mode Register 000357h Timer A1 Mode Register 000358h Timer A2 Mode Register 000359h Timer A3 Mode Register 00035Ah Timer A4 Mode Register 00035Bh Timer B0 Mode Register 00035Ch Timer B1 Mode Register 00035Dh Timer B2 Mode Register 00035Eh Timer B2 Special Mode Register 00035Fh Count Source Prescaler Register 000360h 000361h 000362h 000363h 000364h UART0 Special Mode Register 4 000365h UART0 Special Mode Register 3 000366h UART0 Special Mode Register 2 000367h UART0 Special Mode Register 000368h UART0 Transmit/Receive Mode Register 000369h UART0 Bit Rate Register 00036Ah UART0 Transmit Buffer Register 00036Bh 00036Ch UART0 Transmit/Receive Control Register 0 00036Dh UART0 Transmit/Receive Control Register 1 00036Eh UART0 Receive Buffer Register 00036Fh 000370h 000371h 000372h 000373h 000374h 000375h 000376h 000377h 000378h 000379h 00037Ah 00037Bh 00037Ch CRC Data Register 00037Dh 00037Eh CRC Input Register 00037Fh X: Undefined Blanks are reserved. No access is allowed.
U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
CRCD CRCIN
XXXXh XXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 32 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.15
SFR List (15)
Symbol AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 Reset Value 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh
Address Register 000380h A/D0 Register 0 000381h 000382h A/D0 Register 1 000383h 000384h A/D0 Register 2 000385h 000386h A/D0 Register 3 000387h 000388h A/D0 Register 4 000389h 00038Ah A/D0 Register 5 00038Bh 00038Ch A/D0 Register 6 00038Dh 00038Eh A/D0 Register 7 00038Fh 000390h 000391h 000392h A/D0 Control Register 4 000393h A/D0 Control Register 5 000394h A/D0 Control Register 2 000395h A/D0 Control Register 3 000396h A/D0 Control Register 0 000397h A/D0 Control Register 1 000398h D/A Register 0 000399h 00039Ah D/A Register 1 00039Bh 00039Ch D/A Control Register 00039Dh 00039Eh 00039Fh 0003A0h 0003A1h 0003A2h 0003A3h 0003A4h 0003A5h 0003A6h 0003A7h 0003A8h 0003A9h 0003AAh 0003ABh 0003ACh 0003ADh 0003AEh 0003AFh X: Undefined Blanks are reserved. No access is allowed.
AD0CON4 AD0CON5 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON
XXXX 00XXb 00h X00X X000b XXXX X000b 00h 00h XXh XXh XXXX XX00b
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 33 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.16
SFR List (16)
Symbol Reset Value
Address Register 0003B0h 0003B1h 0003B2h 0003B3h 0003B4h 0003B5h 0003B6h 0003B7h 0003B8h 0003B9h 0003BAh 0003BBh 0003BCh 0003BDh 0003BEh 0003BFh 0003C0h Port P0 Register 0003C1h Port P1 Register 0003C2h Port P0 Direction Register 0003C3h Port P1 Direction Register 0003C4h Port P2 Register 0003C5h Port P3 Register 0003C6h Port P2 Direction Register 0003C7h Port P3 Direction Register 0003C8h Port P4 Register 0003C9h Port P5 Register 0003CAh Port P4 Direction Register 0003CBh Port P5 Direction Register 0003CCh Port P6 Register 0003CDh Port P7 Register 0003CEh Port P6 Direction Register 0003CFh Port P7 Direction Register 0003D0h Port P8 Register 0003D1h Port P9 Register 0003D2h Port P8 Direction Register 0003D3h Port P9 Direction Register 0003D4h Port P10 Register 0003D5h 0003D6h Port P10 Direction Register 0003D7h 0003D8h 0003D9h 0003DAh 0003DBh 0003DCh 0003DDh 0003DEh 0003DFh X: Undefined Blanks are reserved. No access is allowed.
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10
XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00X0 0000b 00h XXh 00h
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 34 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.17
SFR List (17)
Symbol Reset Value
Address Register 0003E0h 0003E1h 0003E2h 0003E3h 0003E4h 0003E5h 0003E6h 0003E7h 0003E8h 0003E9h 0003EAh 0003EBh 0003ECh 0003EDh 0003EEh 0003EFh 0003F0h Pull-up Control Register 0 0003F1h Pull-up Control Register 1 0003F2h Pull-up Control Register 2 0003F3h Pull-up Control Register 3 0003F4h 0003F5h 0003F6h 0003F7h 0003F8h 0003F9h 0003FAh 0003FBh 0003FCh 0003FDh 0003FEh 0003FFh Port Control Register X: Undefined Blanks are reserved. No access is allowed.
PUR0 PUR1 PUR2 PUR3
0000 0000b XXXX 0000b 0000 0000b XXXX XX00b
PCR
XXXX XXX0b
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 35 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.18
SFR List (18)
Symbol FMR0 FMSR0 Reset Value 0X01 XX00b 1000 0000b
Address Register 040000h Flash Memory Control Register 0 040001h Flash Memory Status Register 0 040002h 040003h 040004h 040005h 040006h 040007h 040008h Flash Register Protection Unlock Register 0 040009h Flash Memory Control Register 1 04000Ah Block Protect Bit Monitor Register 0 04000Bh Block Protect Bit Monitor Register 1 04000Ch 04000Dh 04000Eh 04000Fh 040010h 040011h 040012h 040013h 040014h 040015h 040016h 040017h 040018h 040019h 04001Ah 04001Bh 04001Ch 04001Dh 04001Eh 04001Fh 040020h PLL Control Register 0 040021h PLL Control Register 1 040022h 040023h 040024h PLL Status Register 040025h 040026h 040027h 040028h 040029h 04002Ah 04002Bh 04002Ch 04002Dh 04002Eh 04002Fh X: Undefined Blanks are reserved. No access is allowed. Note: 1. The status of protect bit of each block in flash memory is reflected.
FPR0 FMR1 FBPM0 FBPM1
00h 0000 0010b X?X? ????b (1) XXX? ?XXXb (1)
PLC0 PLC1
0000 0001b 0001 1111b
PLS
1XXX XX00b
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 36 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.19
SFR List (19)
Symbol Reset Value
Address Register 040030h to 04003Fh 040040h 040041h 040042h 040043h 040044h Processor Mode Register 0 040045h 040046h System Clock Control Register 0 040047h System Clock Control Register 1 040048h Processor Mode Register 3 040049h 04004Ah Protect Register 04004Bh 04004Ch Protect Register 3 04004Dh Oscillator Stop Detection Register 04004Eh 04004Fh 040050h 040051h 040052h 040053h Processor Mode Register 2 040054h 040055h 040056h 040057h 040058h 040059h 04005Ah Low Speed Mode Clock Control Register 04005Bh 04005Ch 04005Dh 04005Eh 04005Fh 040060h Voltage Regulator Control Register 040061h 040062h Low Voltage Detector Control Register 040063h 040064h Detection Voltage Configuration Register 040065h 040066h 040067h 040068h to 04008Fh X: Undefined Blanks are reserved. No access is allowed.
PM0 CM0 CM1 PM3 PRCR PRCR3 CM2
1000 0000b 0000 1000b 0010 0000b 00h XXXX X000b 0000 0000b 00h
PM2
00h
CM3
XXXX XX00b
VRCR LVDC DVCR
0000 0000b 0000 XX00b 0000 XXXXb
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 37 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.20
SFR List (20)
Symbol Reset Value
Address Register 040090h 040091h 040092h 040093h 040094h 040095h 040096h 040097h Three-phase Output Buffer Control Register 040098h Input Function Select Register 0 040099h Input Function Select Register 1 04009Ah Input Function Select Register 2 04009Bh 04009Ch 04009Dh Input Function Select Register 5 04009Eh Input Function Select Register 6 04009Fh 0400A0h Port P0_0 Port Function Select Register 0400A1h Port P1_0 Port Function Select Register 0400A2h Port P0_1 Port Function Select Register 0400A3h Port P1_1 Port Function Select Register 0400A4h Port P0_2 Port Function Select Register 0400A5h Port P1_2 Port Function Select Register 0400A6h Port P0_3 Port Function Select Register 0400A7h Port P1_3 Port Function Select Register 0400A8h Port P0_4 Port Function Select Register 0400A9h Port P1_4 Port Function Select Register 0400AAh Port P0_5 Port Function Select Register 0400ABh Port P1_5 Port Function Select Register 0400ACh Port P0_6 Port Function Select Register 0400ADh Port P1_6 Port Function Select Register 0400AEh Port P0_7 Port Function Select Register 0400AFh Port P1_7 Port Function Select Register 0400B0h Port P2_0 Port Function Select Register 0400B1h Port P3_0 Port Function Select Register 0400B2h Port P2_1 Port Function Select Register 0400B3h Port P3_1 Port Function Select Register 0400B4h Port P2_2 Port Function Select Register 0400B5h Port P3_2 Port Function Select Register 0400B6h Port P2_3 Port Function Select Register 0400B7h Port P3_3 Port Function Select Register 0400B8h Port P2_4 Port Function Select Register 0400B9h Port P3_4 Port Function Select Register 0400BAh Port P2_5 Port Function Select Register 0400BBh Port P3_5 Port Function Select Register 0400BCh Port P2_6 Port Function Select Register 0400BDh Port P3_6 Port Function Select Register 0400BEh Port P2_7 Port Function Select Register 0400BFh Port P3_7 Port Function Select Register X: Undefined Blanks are reserved. No access is allowed.
IOBC IFS0 IFS1 IFS2
0XXX XX0Xb X000 X000b XXXX X0X0b 0000 0000b
IFS5 IFS6 P0_0S P1_0S P0_1S P1_1S P0_2S P1_2S P0_3S P1_3S P0_4S P1_4S P0_5S P1_5S P0_6S P1_6S P0_7S P1_7S P2_0S P3_0S P2_1S P3_1S P2_2S P3_2S P2_3S P3_3S P2_4S P3_4S P2_5S P3_5S P2_6S P3_6S P2_7S P3_7S
XXX0 X0X0b XXXX 0000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 38 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.21
SFR List (21)
Symbol P4_0S P5_0S P4_1S P5_1S P4_2S P5_2S P4_3S P5_3S P4_4S P5_4S P4_5S P5_5S P4_6S P5_6S P4_7S P5_7S P6_0S P7_0S P6_1S P7_1S P6_2S P7_2S P6_3S P7_3S P6_4S P7_4S P6_5S P7_5S P6_6S P7_6S P6_7S P7_7S P8_0S P8_1S P8_2S P8_3S P9_3S P8_4S P9_4S P9_5S P8_6S P9_6S P8_7S P9_7S Reset Value XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b XXXX X000b
Address Register 0400C0h Port P4_0 Port Function Select Register 0400C1h Port P5_0 Port Function Select Register 0400C2h Port P4_1 Port Function Select Register 0400C3h Port P5_1 Port Function Select Register 0400C4h Port P4_2 Port Function Select Register 0400C5h Port P5_2 Port Function Select Register 0400C6h Port P4_3 Port Function Select Register 0400C7h Port P5_3 Port Function Select Register 0400C8h Port P4_4 Port Function Select Register 0400C9h Port P5_4 Port Function Select Register 0400CAh Port P4_5 Port Function Select Register 0400CBh Port P5_5 Port Function Select Register 0400CCh Port P4_6 Port Function Select Register 0400CDh Port P5_6 Port Function Select Register 0400CEh Port P4_7 Port Function Select Register 0400CFh Port P5_7 Port Function Select Register 0400D0h Port P6_0 Port Function Select Register 0400D1h Port P7_0 Port Function Select Register 0400D2h Port P6_1 Port Function Select Register 0400D3h Port P7_1 Port Function Select Register 0400D4h Port P6_2 Port Function Select Register 0400D5h Port P7_2 Port Function Select Register 0400D6h Port P6_3 Port Function Select Register 0400D7h Port P7_3 Port Function Select Register 0400D8h Port P6_4 Port Function Select Register 0400D9h Port P7_4 Port Function Select Register 0400DAh Port P6_5 Port Function Select Register 0400DBh Port P7_5 Port Function Select Register 0400DCh Port P6_6 Port Function Select Register 0400DDh Port P7_6 Port Function Select Register 0400DEh Port P6_7 Port Function Select Register 0400DFh Port P7_7 Port Function Select Register 0400E0h Port P8_0 Port Function Select Register 0400E1h 0400E2h Port P8_1 Port Function Select Register 0400E3h 0400E4h Port P8_2 Port Function Select Register 0400E5h 0400E6h Port P8_3 Port Function Select Register 0400E7h Port P9_3 Port Function Select Register 0400E8h Port P8_4 Port Function Select Register 0400E9h Port P9_4 Port Function Select Register 0400EAh 0400EBh Port P9_5 Port Function Select Register 0400ECh Port P8_6 Port Function Select Register 0400EDh Port P9_6 Port Function Select Register 0400EEh Port P8_7 Port Function Select Register 0400EFh Port P9_7 Port Function Select Register X: Undefined Blanks are reserved. No access is allowed.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 39 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.22
SFR List (22)
Symbol P10_0S P10_1S P10_2S P10_3S P10_4S P10_5S P10_6S P10_7S Reset Value 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b
Address Register 0400F0h Port P10_0 Port Function Select Register 0400F1h 0400F2h Port P10_1 Port Function Select Register 0400F3h 0400F4h Port P10_2 Port Function Select Register 0400F5h 0400F6h Port P10_3 Port Function Select Register 0400F7h 0400F8h Port P10_4 Port Function Select Register 0400F9h 0400FAh Port P10_5 Port Function Select Register 0400FBh 0400FCh Port P10_6 Port Function Select Register 0400FDh 0400FEh Port P10_7 Port Function Select Register 0400FFh 040100h 040101h 040102h 040103h 040104h 040105h 040106h 040107h 040108h 040109h 04010Ah 04010Bh 04010Ch 04010Dh 04010Eh 04010Fh 040110h 040111h 040112h 040113h 040114h 040115h 040116h 040117h 040118h 040119h 04011Ah 04011Bh 04011Ch 04011Dh 04011Eh 04011Fh X: Undefined Blanks are reserved. No access is allowed.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 40 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.23
SFR List (23)
Symbol Reset Value
Address Register 040120h to 04403Fh 044040h 044041h 044042h 044043h 044044h 044045h 044046h 044047h 044048h 044049h 04404Ah 04404Bh 04404Ch Protect Register 4 04404Dh Watchdog Timer Clock Control Register 04404Eh Watchdog Timer Start Register 04404Fh Watchdog Timer Control Register 044050h 044051h 044052h 044053h 044054h 044055h 044056h 044057h 044058h 044059h 04405Ah 04405Bh 04405Ch 04405Dh 04405Eh 04405Fh Protect Register 2 X: Undefined Blanks are reserved. No access is allowed.
PRCR4 WDK WDTS WDC
0000 0000b 0000 0000b XXXX XXXXb 000X XXXXb
PRCR2
0XXX XXXXb
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 41 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.24
SFR List (24)
Symbol Reset Value
Address Register 044060h 044061h 044062h 044063h 044064h 044065h 044066h 044067h 044068h 044069h 04406Ah 04406Bh 04406Ch 04406Dh 04406Eh 04406Fh External Interrupt Source Select Register 0 044070h DMA0 Request Source Select Register 2 044071h DMA1 Request Source Select Register 2 044072h DMA2 Request Source Select Register 2 044073h DMA3 Request Source Select Register 2 044074h 044075h 044076h 044077h 044078h DMA0 Request Source Select Register 1 044079h DMA1 Request Source Select Register 1 04407Ah DMA2 Request Source Select Register 1 04407Bh DMA3 Request Source Select Register 1 04407Ch 04407Dh Wake-up/Interrupt Priority Level Control Register 2 04407Eh 04407Fh Wake-up/Interrupt Priority Level Control Register 1 044080h External Interrupt Input Filter Select Register 0 044081h 044082h External Interrupt Input Filter Select Register 1 044083h 044084h 044085h 044086h 044087h 044088h 044089h 04408Ah 04408Bh 04408Ch 04408Dh 04408Eh 04408Fh X: Undefined Blanks are reserved. No access is allowed.
IFSR0 DM0SL2 DM1SL2 DM2SL2 DM3SL2
0000 0000b XX00 0000b XX00 0000b XX00 0000b XX00 0000b
DM0SL DM1SL DM2SL DM3SL RIPL2 RIPL1 INTF0 INTF1
XXX0 0000b XXX0 0000b XXX0 0000b XXX0 0000b XX0X 0000b XX0X 0000b 0000 0000b 0000 0000b
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 42 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.25
SFR List (25)
Symbol Reset Value
Address Register 044090h to 044DFFh 044E00h LIN Channel Window Select/Input Signal Low Detection Status Register 044E01h LIN Baud Rate Generator Control Register 044E02h LIN Baud Rate Prescaler 0 044E03h LIN Baud Rate Prescaler 1 044E04h LIN Mode Register 0 044E05h LIN Mode Register 1 044E06h LIN Wake-up Setting Register 044E07h 044E08h LIN Break Field Setting Register 044E09h LIN Space Setting Register 044E0Ah LIN Response Field Setting Register 044E0Bh LIN ID Buffer Register 044E0Ch LIN Status Control Register 044E0Dh LIN Transmission Control Register 044E0Eh LIN Status Register 044E0Fh LIN Error Status Register 044E10h LIN Data 1 Buffer Register 044E11h LIN Data 2 Buffer Register 044E12h LIN Data 3 Buffer Register 044E13h LIN Data 4 Buffer Register 044E14h LIN Data 5 Buffer Register 044E15h LIN Data 6 Buffer Register 044E16h LIN Data 7 Buffer Register 044E17h LIN Data 8 Buffer Register 044E18h 044E19h 044E1Ah 044E1Bh 044E1Ch 044E1Dh 044E1Eh 044E1Fh X: Undefined Blanks are reserved. No access is allowed.
LCW LBRG LBRP0 LBRP1 LMD0 LMD1 LWUP LBRK LSPC LRFC LIDB LSC LTC LST LEST LDB1 LDB2 LDB3 LDB4 LDB5 LDB6 LDB7 LDB8
0000 XX00b XXX0 XX00b 00h 00h 0000 0X00b 00h 00h XX00 0000b XX00 X000b XX00 0000b 00h XXXX XX00b XXXX XX00b XX00 0000b X000 0000b 00h 00h 00h 00h 00h 00h 00h 00h
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 43 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.26
SFR List (26)
Symbol Reset Value
Address Register 044E20h to 044EFFh 044F00h 044F01h 044F02h 044F03h 044F04h 044F05h 044F06h SS0 Receive Data Register 044F07h SS0 Receive Data Register (H) 044F08h SS0 Control Register H 044F09h SS0 Control Register L 044F0Ah SS0 Mode Register 044F0Bh SS0 Enable Register 044F0Ch SS0 Status Register 044F0Dh SS0 Mode Register 2 044F0Eh SS0 Transmit Data Register 044F0Fh SS0 Transmit Data Register (H) 044F10h 044F11h 044F12h 044F13h 044F14h 044F15h 044F16h 044F17h 044F18h 044F19h 044F1Ah 044F1Bh 044F1Ch 044F1Dh 044F1Eh 044F1Fh 044F20h 044F21h 044F22h 044F23h 044F24h 044F25h 044F26h 044F27h X: Undefined Blanks are reserved. No access is allowed.
SS0RDR SS0RDR (H) SS0CRH SS0CRL SS0MR SS0ER SS0SR SS0MR2 SS0TDR SS0TDR (H)
FFh FFh 00h 0111 1101b 0001 0000b 00h 00h 00h FFh FFh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 44 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.27
SFR List (27)
Symbol Reset Value
Address Register 044F28h to 044FDFh 044FE0h E2dataFlash Address Register 044FE1h 044FE2h 044FE3h 044FE4h 044FE5h 044FE6h 044FE7h 044FE8h E2dataFlash Instruction Register 044FE9h 044FEAh 044FEBh 044FECh E2dataFlash Data Register 044FEDh 044FEEh 044FEFh 044FF0h E2dataFlash Mode Register 044FF1h 044FF2h E2dataFlash Control Register 044FF3h 044FF4h E2dataFlash Status Register 1 044FF5h 044FF6h 044FF7h 044FF8h 044FF9h 044FFAh 044FFBh 044FFCh 044FFDh 044FFEh 044FFFh 045000h 045001h E2dataFlash Status Register 0 045002h 045003h 045004h 045005h 045006h 045007h 045008h to 045FFFh 046000h to 0467FFh X: Undefined Blanks are reserved. No access is allowed.
E2FA
XXXX 0000h
E2FI
XX00h
E2FD
XXXXh
E2FM E2FC E2FS1
0000 0000b XXXX XXX0b XXXX XXX0b
E2FS0
XXXX XXXXb
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 45 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.28
SFR List (28)
Symbol Reset Value
Address Register 046800h to 047BFFh 047C00h CAN0 Mailbox 0: Message Identifier 047C01h 047C02h 047C03h 047C04h 047C05h CAN0 Mailbox 0: Data Length 047C06h CAN0 Mailbox 0: Data Field 047C07h 047C08h 047C09h 047C0Ah 047C0Bh 047C0Ch 047C0Dh 047C0Eh CAN0 Mailbox 0: Time Stamp 047C0Fh 047C10h CAN0 Mailbox 1: Message Identifier 047C11h 047C12h 047C13h 047C14h 047C15h CAN0 Mailbox 1: Data Length 047C16h CAN0 Mailbox 1: Data Field 047C17h 047C18h 047C19h 047C1Ah 047C1Bh 047C1Ch 047C1Dh 047C1Eh CAN0 Mailbox 1: Time Stamp 047C1Fh 047C20h CAN0 Mailbox 2: Message Identifier 047C21h 047C22h 047C23h 047C24h 047C25h CAN0 Mailbox 2: Data Length 047C26h CAN0 Mailbox 2: Data Field 047C27h 047C28h 047C29h 047C2Ah 047C2Bh 047C2Ch 047C2Dh 047C2Eh CAN0 Mailbox 2: Time Stamp 047C2Fh X: Undefined Blanks are reserved. No access is allowed.
C0MB0
XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB1 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB2 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 46 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.29
SFR List (29)
Symbol C0MB3 Reset Value XXXX XXXXh
Address Register 047C30h CAN0 Mailbox 3: Message Identifier 047C31h 047C32h 047C33h 047C34h 047C35h CAN0 Mailbox 3: Data Length 047C36h CAN0 Mailbox 3: Data Field 047C37h 047C38h 047C39h 047C3Ah 047C3Bh 047C3Ch 047C3Dh 047C3Eh CAN0 Mailbox 3: Time Stamp 047C3Fh 047C40h CAN0 Mailbox 4: Message Identifier 047C41h 047C42h 047C43h 047C44h 047C45h CAN0 Mailbox 4: Data Length 047C46h CAN0 Mailbox 4: Data Field 047C47h 047C48h 047C49h 047C4Ah 047C4Bh 047C4Ch 047C4Dh 047C4Eh CAN0 Mailbox 4: Time Stamp 047C4Fh 047C50h CAN0 Mailbox 5: Message Identifier 047C51h 047C52h 047C53h 047C54h 047C55h CAN0 Mailbox 5: Data Length 047C56h CAN0 Mailbox 5: Data Field 047C57h 047C58h 047C59h 047C5Ah 047C5Bh 047C5Ch 047C5Dh 047C5Eh CAN0 Mailbox 5: Time Stamp 047C5Fh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB4 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB5 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 47 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.30
SFR List (30)
Symbol C0MB6 Reset Value XXXX XXXXh
Address Register 047C60h CAN0 Mailbox 6: Message Identifier 047C61h 047C62h 047C63h 047C64h 047C65h CAN0 Mailbox 6: Data Length 047C66h CAN0 Mailbox 6: Data Field 047C67h 047C68h 047C69h 047C6Ah 047C6Bh 047C6Ch 047C6Dh 047C6Eh CAN0 Mailbox 6: Time Stamp 047C6Fh 047C70h CAN0 Mailbox 7: Message Identifier 047C71h 047C72h 047C73h 047C74h 047C75h CAN0 Mailbox 7: Data Length 047C76h CAN0 Mailbox 7: Data Field 047C77h 047C78h 047C79h 047C7Ah 047C7Bh 047C7Ch 047C7Dh 047C7Eh CAN0 Mailbox 7: Time Stamp 047C7Fh 047C80h CAN0 Mailbox 8: Message Identifier 047C81h 047C82h 047C83h 047C84h 047C85h CAN0 Mailbox 8: Data Length 047C86h CAN0 Mailbox 8: Data Field 047C87h 047C88h 047C89h 047C8Ah 047C8Bh 047C8Ch 047C8Dh 047C8Eh CAN0 Mailbox 8:Time Stamp 047C8Fh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB7 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB8 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 48 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.31
SFR List (31)
Symbol C0MB9 Reset Value XXXX XXXXh
Address Register 047C90h CAN0 Mailbox 9: Message Identifier 047C91h 047C92h 047C93h 047C94h 047C95h CAN0 Mailbox 9: Data Length 047C96h CAN0 Mailbox 9: Data Field 047C97h 047C98h 047C99h 047C9Ah 047C9Bh 047C9Ch 047C9Dh 047C9Eh CAN0 Mailbox 9: Time Stamp 047C9Fh 047CA0h CAN0 Mailbox 10: Message Identifier 047CA1h 047CA2h 047CA3h 047CA4h 047CA5h CAN0 Mailbox 10: Data Length 047CA6h CAN0 Mailbox 10: Data Field 047CA7h 047CA8h 047CA9h 047CAAh 047CABh 047CACh 047CADh 047CAEh CAN0 Mailbox 10: Time Stamp 047CAFh 047CB0h CAN0 Mailbox 11: Message Identifier 047CB1h 047CB2h 047CB3h 047CB4h 047CB5h CAN0 Mailbox 11: Data Length 047CB6h CAN0 Mailbox 11: Data Field 047CB7h 047CB8h 047CB9h 047CBAh 047CBBh 047CBCh 047CBDh 047CBEh CAN0 Mailbox 11: Time Stamp 047CBFh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB10 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB11 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 49 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.32
SFR List (32)
Symbol C0MB12 Reset Value XXXX XXXXh
Address Register 047CC0h CAN0 Mailbox 12: Message Identifier 047CC1h 047CC2h 047CC3h 047CC4h 047CC5h CAN0 Mailbox 12: Data Length 047CC6h CAN0 Mailbox 12: Data Field 047CC7h 047CC8h 047CC9h 047CCAh 047CCBh 047CCCh 047CCDh 047CCEh CAN0 Mailbox 12: Time Stamp 047CCFh 047CD0h CAN0 Mailbox 13: Message Identifier 047CD1h 047CD2h 047CD3h 047CD4h 047CD5h CAN0 Mailbox 13: Data Length 047CD6h CAN0 Mailbox 13: Data Field 047CD7h 047CD8h 047CD9h 047CDAh 047CDBh 047CDCh 047CDDh 047CDEh CAN0 Mailbox 13: Time Stamp 047CDFh 047CE0h CAN0 Mailbox 14: Message Identifier 047CE1h 047CE2h 047CE3h 047CE4h 047CE5h CAN0 Mailbox 14: Data Length 047CE6h CAN0 Mailbox 14: Data Field 047CE7h 047CE8h 047CE9h 047CEAh 047CEBh 047CECh 047CEDh 047CEEh CAN0 Mailbox 14: Time Stamp 047CEFh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB13 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB14 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 50 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.33
SFR List (33)
Symbol C0MB15 Reset Value XXXX XXXXh
Address Register 047CF0h CAN0 Mailbox 15: Message Identifier 047CF1h 047CF2h 047CF3h 047CF4h 047CF5h CAN0 Mailbox 15: Data Length 047CF6h CAN0 Mailbox 15: Data Field 047CF7h 047CF8h 047CF9h 047CFAh 047CFBh 047CFCh 047CFDh 047CFEh CAN0 Mailbox 15: Time Stamp 047CFFh 047D00h CAN0 Mailbox 16: Message Identifier 047D01h 047D02h 047D03h 047D04h 047D05h CAN0 Mailbox 16: Data Length 047D06h CAN0 Mailbox 16: Data Field 047D07h 047D08h 047D09h 047D0Ah 047D0Bh 047D0Ch 047D0Dh 047D0Eh CAN0 Mailbox 16: Time Stamp 047D0Fh 047D10h CAN0 Mailbox 17: Message Identifier 047D11h 047D12h 047D13h 047D14h 047D15h CAN0 Mailbox 17: Data Length 047D16h CAN0 Mailbox 17: Data Field 047D17h 047D18h 047D19h 047D1Ah 047D1Bh 047D1Ch 047D1Dh 047D1Eh CAN0 Mailbox 17: Time Stamp 047D1Fh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB16 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB17 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 51 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.34
SFR List (34)
Symbol C0MB18 Reset Value XXXX XXXXh
Address Register 047D20h CAN0 Mailbox 18: Message Identifier 047D21h 047D22h 047D23h 047D24h 047D25h CAN0 Mailbox 18: Data Length 047D26h CAN0 Mailbox 18: Data Field 047D27h 047D28h 047D29h 047D2Ah 047D2Bh 047D2Ch 047D2Dh 047D2Eh CAN0 Mailbox 18: Time Stamp 047D2Fh 047D30h CAN0 Mailbox 19: Message Identifier 047D31h 047D32h 047D33h 047D34h 047D35h CAN0 Mailbox 19: Data Length 047D36h CAN0 Mailbox 19: Data Field 047D37h 047D38h 047D39h 047D3Ah 047D3Bh 047D3Ch 047D3Dh 047D3Eh CAN0 Mailbox 19: Time Stamp 047D3Fh 047D40h CAN0 Mailbox 20: Message Identifier 047D41h 047D42h 047D43h 047D44h 047D45h CAN0 Mailbox 20: Data Length 047D46h CAN0 Mailbox 20: Data Field 047D47h 047D48h 047D49h 047D4Ah 047D4Bh 047D4Ch 047D4Dh 047D4Eh CAN0 Mailbox 20: Time Stamp 047D4Fh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB19 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB20 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 52 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.35
SFR List (35)
Symbol C0MB21 Reset Value XXXX XXXXh
Address Register 047D50h CAN0 Mailbox 21: Message Identifier 047D51h 047D52h 047D53h 047D54h 047D55h CAN0 Mailbox 21: Data Length 047D56h CAN0 Mailbox 21: Data Field 047D57h 047D58h 047D59h 047D5Ah 047D5Bh 047D5Ch 047D5Dh 047D5Eh CAN0 Mailbox 21: Time Stamp 047D5Fh 047D60h CAN0 Mailbox 22: Message Identifier 047D61h 047D62h 047D63h 047D64h 047D65h CAN0 Mailbox 22: Data Length 047D66h CAN0 Mailbox 22: Data Field 047D67h 047D68h 047D69h 047D6Ah 047D6Bh 047D6Ch 047D6Dh 047D6Eh CAN0 Mailbox 22: Time Stamp 047D6Fh 047D70h CAN0 Mailbox 23: Message Identifier 047D71h 047D72h 047D73h 047D74h 047D75h CAN0 Mailbox 23: Data Length 047D76h CAN0 Mailbox 23: Data Field 047D77h 047D78h 047D79h 047D7Ah 047D7Bh 047D7Ch 047D7Dh 047D7Eh CAN0 Mailbox 23: Time Stamp 047D7Fh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB22 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB23 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 53 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.36
SFR List (36)
Symbol C0MB24 Reset Value XXXX XXXXh
Address Register 047D80h CAN0 Mailbox 24: Message Identifier 047D81h 047D82h 047D83h 047D84h 047D85h CAN0 Mailbox 24: Data Length 047D86h CAN0 Mailbox 24: Data Field 047D87h 047D88h 047D89h 047D8Ah 047D8Bh 047D8Ch 047D8Dh 047D8Eh CAN0 Mailbox 24: Time Stamp 047D8Fh 047D90h CAN0 Mailbox 25: Message Identifier 047D91h 047D92h 047D93h 047D94h 047D95h CAN0 Mailbox 25: Data Length 047D96h CAN0 Mailbox 25: Data Field 047D97h 047D98h 047D99h 047D9Ah 047D9Bh 047D9Ch 047D9Dh 047D9Eh CAN0 Mailbox 25: Time Stamp 047D9Fh 047DA0h CAN0 Mailbox 26: Message Identifier 047DA1h 047DA2h 047DA3h 047DA4h 047DA5h CAN0 Mailbox 26: Data Length 047DA6h CAN0 Mailbox 26: Data Field 047DA7h 047DA8h 047DA9h 047DAAh 047DABh 047DACh 047DADh 047DAEh CAN0 Mailbox 26: Time Stamp 047DAFh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB25 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB26 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 54 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.37
SFR List (37)
Symbol C0MB27 Reset Value XXXX XXXXh
Address Register 047DB0h CAN0 Mailbox 27: Message Identifier 047DB1h 047DB2h 047DB3h 047DB4h 047DB5h CAN0 Mailbox 27: Data Length 047DB6h CAN0 Mailbox 27: Data Field 047DB7h 047DB8h 047DB9h 047DBAh 047DBBh 047DBCh 047DBDh 047DBEh CAN0 Mailbox 27: Time Stamp 047DBFh 047DC0h CAN0 Mailbox 28: Message Identifier 047DC1h 047DC2h 047DC3h 047DC4h 047DC5h CAN0 Mailbox 28: Data Length 047DC6h CAN0 Mailbox 28: Data Field 047DC7h 047DC8h 047DC9h 047DCAh 047DCBh 047DCCh 047DCDh 047DCEh CAN0 Mailbox 28: Time Stamp 047DCFh 047DD0h CAN0 Mailbox 29: Message Identifier 047DD1h 047DD2h 047DD3h 047DD4h 047DD5h CAN0 Mailbox 29: Data Length 047DD6h CAN0 Mailbox 29: Data Field 047DD7h 047DD8h 047DD9h 047DDAh 047DDBh 047DDCh 047DDDh 047DDEh CAN0 Mailbox 29: Time Stamp 047DDFh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB28 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB29 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 55 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.38
SFR List (38)
Symbol C0MB30 Reset Value XXXX XXXXh
Address Register 047DE0h CAN0 Mailbox 30: Message Identifier 047DE1h 047DE2h 047DE3h 047DE4h 047DE5h CAN0 Mailbox 30: Data Length 047DE6h CAN0 Mailbox 30: Data Field 047DE7h 047DE8h 047DE9h 047DEAh 047DEBh 047DECh 047DEDh 047DEEh CAN0 Mailbox 30: Time Stamp 047DEFh 047DF0h CAN0 Mailbox 31: Message Identifier 047DF1h 047DF2h 047DF3h 047DF4h 047DF5h CAN0 Mailbox 31: Data Length 047DF6h CAN0 Mailbox 31: Data Field 047DF7h 047DF8h 047DF9h 047DFAh 047DFBh 047DFCh 047DFDh 047DFEh CAN0 Mailbox 31: Time Stamp 047DFFh 047E00h CAN0 Acceptance Mask Register 0 047E01h 047E02h 047E03h 047E04h CAN0 Acceptance Mask Register 1 047E05h 047E06h 047E07h 047E08h CAN0 Acceptance Mask Register 2 047E09h 047E0Ah 047E0Bh 047E0Ch CAN0 Acceptance Mask Register 3 047E0Dh 047E0Eh 047E0Fh X: Undefined Blanks are reserved. No access is allowed.
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MB31 XXXX XXXXh
XXh XXXX XXXX XXXX XXXXh
XXXXh C0MKR0 XXXX XXXXh
C0MKR1
XXXX XXXXh
C0MKR2
XXXX XXXXh
C0MKR3
XXXX XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 56 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.39
SFR List (39)
Symbol C0MKR4 Reset Value XXXX XXXXh
Address Register 047E10h CAN0 Acceptance Mask Register 4 047E11h 047E12h 047E13h 047E14h CAN0 Acceptance Mask Register 5 047E15h 047E16h 047E17h 047E18h CAN0 Acceptance Mask Register 6 047E19h 047E1Ah 047E1Bh 047E1Ch CAN0 Acceptance Mask Register 7 047E1Dh 047E1Eh 047E1Fh 047E20h CAN0 FIFO Receive ID Compare Register 0 047E21h 047E22h 047E23h 047E24h CAN0 FIFO Receive ID Compare Register 1 047E25h 047E26h 047E27h 047E28h CAN0 Mask Invalid Register 047E29h 047E2Ah 047E2Bh 047E2Ch CAN0 Mailbox Interrupt Enable Register 047E2Dh 047E2Eh 047E2Fh 047E30h 047E31h 047E32h 047E33h 047E34h 047E35h 047E36h 047E37h 047E38h 047E39h 047E3Ah 047E3Bh 047E3Ch 047E3Dh 047E3Eh 047E3Fh 047E40h to 047F1Fh X: Undefined Blanks are reserved. No access is allowed.
C0MKR5
XXXX XXXXh
C0MKR6
XXXX XXXXh
C0MKR7
XXXX XXXXh
C0FIDCR0
XXXX XXXXh
C0FIDCR1
XXXX XXXXh
C0MKIVLR
XXXX XXXXh
C0MIER
XXXX XXXXh
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 57 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.40
SFR List (40)
Symbol C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0MCTL16 C0MCTL17 C0MCTL18 C0MCTL19 C0MCTL20 C0MCTL21 C0MCTL22 C0MCTL23 C0MCTL24 C0MCTL25 C0MCTL26 C0MCTL27 C0MCTL28 C0MCTL29 C0MCTL30 C0MCTL31 Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Address Register 047F20h CAN0 Message Control Register 0 047F21h CAN0 Message Control Register 1 047F22h CAN0 Message Control Register 2 047F23h CAN0 Message Control Register 3 047F24h CAN0 Message Control Register 4 047F25h CAN0 Message Control Register 5 047F26h CAN0 Message Control Register 6 047F27h CAN0 Message Control Register 7 047F28h CAN0 Message Control Register 8 047F29h CAN0 Message Control Register 9 047F2Ah CAN0 Message Control Register 10 047F2Bh CAN0 Message Control Register 11 047F2Ch CAN0 Message Control Register 12 047F2Dh CAN0 Message Control Register 13 047F2Eh CAN0 Message Control Register 14 047F2Fh CAN0 Message Control Register 15 047F30h CAN0 Message Control Register 16 047F31h CAN0 Message Control Register 17 047F32h CAN0 Message Control Register 18 047F33h CAN0 Message Control Register 19 047F34h CAN0 Message Control Register 20 047F35h CAN0 Message Control Register 21 047F36h CAN0 Message Control Register 22 047F37h CAN0 Message Control Register 23 047F38h CAN0 Message Control Register 24 047F39h CAN0 Message Control Register 25 047F3Ah CAN0 Message Control Register 26 047F3Bh CAN0 Message Control Register 27 047F3Ch CAN0 Message Control Register 28 047F3Dh CAN0 Message Control Register 29 047F3Eh CAN0 Message Control Register 30 047F3Fh CAN0 Message Control Register 31 X: Undefined Blanks are reserved. No access is allowed.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 58 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
4. Special Function Registers (SFR)
Table 4.41
SFR List (41)
Symbol C0CTLR C0STR C0BCR Reset Value 0000 0101b 0000 0000b 0000 0101b 0000 0000b 00 0000h
Address Register 047F40h CAN0 Control Register 047F41h 047F42h CAN0 Status Register 047F43h 047F44h CAN0 Bit Configuration Register 047F45h 047F46h 047F47h CAN0 Clock Select Register 047F48h CAN0 Receive FIFO Control Register 047F49h CAN0 Receive FIFO Pointer Control Register 047F4Ah CAN0 Transmit FIFO Control Register 047F4Bh CAN0 Transmit FIFO Pointer Control Register 047F4Ch CAN0 Error Interrupt Enable Register 047F4Dh CAN0 Error Interrupt Factor Judge Register 047F4Eh CAN0 Reception Error Count Register 047F4Fh CAN0 Transmission Error Count Register 047F50h CAN0 Error Code Store Register 047F51h CAN0 Channel Search Support Register 047F52h CAN0 Mailbox Search Status Register 047F53h CAN0 Mailbox Search Mode Register 047F54h CAN0 Time Stamp Register 047F55h 047F56h CAN0 Acceptance Filter Support Register 047F57h 047F58h CAN0 Test Control Register 047F59h 047F5Ah 047F5Bh 047F5Ch 047F5Dh 047F5Eh 047F5Fh 047F60h to 047FFFh 048000h to 04FFFFh X: Undefined Blanks are reserved. No access is allowed.
C0CLKR C0RFCR C0RFPCR C0TFCR C0TFPCR C0EIER C0EIFR C0RECR C0TECR C0ECSR C0CSSR C0MSSR C0MSMR C0TSR C0AFSR C0TCR
00h 1000 0000b XXh 1000 0000b XXh 00h 00h 00h 00h 00h XXh 1000 0000b XXXX XX00b 0000h XXXXh 00h
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 59 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
5.
Electrical Characteristics
Absolute Maximum Ratings (1)
Table 5.1
Symbol VCC AVCC VI Supply voltage
Characteristic Analog supply voltage Input voltage XIN, RESET, CNVSS, NSD VREF, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 XOUT, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
Condition VCC = AVCC VCC = AVCC
Value -0.3 to 6.0 -0.3 to 6.0
Unit V V
-0.3 to VCC + 0.3
V
VO
Output voltage
-0.3 to VCC + 0.3
V
Pd -- Tstg
Power consumption Operating temperature range Storage temperature range
Ta = 25C
500 -40 to 125 -65 to 150
mW C C
Note: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 60 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Table 5.2
Operating Conditions (1) (1)
Symbol VCC AVCC VREF VSS AVSS VIH
Characteristic Digital supply voltage Analog supply voltage Reference voltage Digital ground voltage Analog ground voltage
Value Min. 3.0 3.0 0 0 VCC Typ. 5.0
VCC
Max. 5.5 VCC
Unit V V V V V V
High level XIN, RESET, CNVSS, NSD 0.8 x VCC input voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 0.7 x VCC to P5_7, P6_0 to P6_7, P7_0 to P7_7, (2), P9_1, P9_3 to P9_7, P8_0 to P8_7 P10_0 to P10_7 Low level XIN, RESET, CNVSS, NSD input voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7 (2), P9_1, P9_3 to P9_7, P10_0 to P10_7 Operating Version J temperature Version L range Version K 0
VCC
V
VIL
0.2 x VCC
V
0
0.3 x VCC
V
Topr
-40 -40 -40
85 105 125
C C C
Notes: 1. The device is operationally guaranteed under these operating conditions. 2. VIH and VIL for P8_7 are specified for P8_7 as a programmable port. These values are not applicable to P8_7 as XCIN.
Table 5.3 Operating Conditions (2) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol CVDC
Characteristic Decoupling capacitance of voltage regulator Inter-pin voltage: 1.5 V
Value Min. 2.4 Typ. Max. 10.0
Unit F
Note: 1. The device is operationally guaranteed under these operating conditions.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 61 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Table 5.4
Operating Conditions (3) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol IOH(peak) High level peak output current (2) High level average output current (3) Low level peak output current (2) Low level average output current (3)
Characteristic P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
Value Min. Typ. Max. -10.0
Unit
mA
IOH(avg)
-5.0
mA
IOL(peak)
10.0
mA
IOL(avg)
5.0
mA
Notes: 1. The device is operationally guaranteed under these operating conditions. 2. The following conditions should be satisfied: * The sum of IOL(peak) of pots P0, P1, P2, P8_6, P8_7, P9, and P10 is 80 mA or less. * The sum of IOL(peak) of ports P3, P4, P5, P6, P7, and P8_0 to P8_4 is 80 mA or less. * The sum of IOH(peak) of ports P1 and P2 is -40 mA or less. * The sum of IOH(peak) of ports P0 and P10 is -40 mA or less. * The sum of IOH(peak) of ports P3, P4, P5, and P6 is -40 mA or less. * The sum of IOH(peak) of ports P7, P8, and P9 is -40 mA or less. 3. Average value within 100 ms.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 62 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Table 5.5
Operating Conditions (4) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol f(XIN) f(XRef) f(PLL) f(Base) tc(Base) f(CPU) tc(CPU) f(BCLK) tc(BCLK) f(PER) f(XCIN)
Characteristic Main clock oscillator frequency Reference clock frequency PLL clock oscillator frequency Base clock frequency Base clock cycle time CPU operating frequency CPU clock cycle time Peripheral bus clock operating frequency Peripheral bus clock cycle time Peripheral clock source frequency Sub clock oscillator frequency
Value Min. 4 2 96 15.625 64 15.625 32 31.25 32 32.768 50 Typ. Max. 8 4 144 64
Unit MHz MHz MHz MHz ns MHz ns MHz ns MHz kHz
Note: 1. The device is operationally guaranteed under these operating conditions.
t c(Base)
Base clock (Internal signal)
t c(CPU)
CPU clock (Internal signal)
t c(BCLK)
Peripheral bus clock (Internal signal)
Figure 5.1
Clock Cycle Time
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 63 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Table 5.6
Operating Conditions (5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1, 2)
Symbol IIC(H) High input injection current
Characteristic P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_5, P7_7, P8_0 to P8_5, P9_3 to P9_6, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_5, P7_7, P8_0 to P8_5, P9_3 to P9_6, P10_0 to P10_7
Value Measurement Unit Condition Min. Typ. Max.
VI > VCC
2
mA
IIC(L)
Low input injection current
VI < VSS
-2
mA
|IIC|
Total injection current
20
mA
Notes: 1. The device is operationally guaranteed under these operating conditions. 2. These conditions are applicable when each port is designated as input.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 64 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Table 5.7
Operating Conditions (6) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol Vr(VCC) Allowable ripple voltage
Characteristic VCC = 5.0 V VCC = 3.0 V VCC = 5.0 V VCC = 3.0 V
Value Min. Typ. Max. 0.5 0.3 0.3 0.3 10
Unit Vp-p Vp-p V/ms V/ms kHz
dVr(VCC)/dt Ripple voltage gradient fr(VCC) Allowable ripple frequency
Note: 1. The device is operationally guaranteed under these operating conditions.
1 / f r(VCC)
VCC
V r(VCC)
Figure 5.2
Ripple Waveform
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 65 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Table 5.8
Flash Memory Electrical Characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol -- -- --
Characteristic Programming and erasure endurance of flash Program area memory (1) Data area 4-word program time Lock bit-program time Block erasure time Program area Data area Program area Data area 4 Kbyte block 32 Kbyte block 64 Kbyte block Flash memory circuit start-up stabilization time
Value Min. 1000 10000 150 300 70 140 0.12 0.17 0.20 20 900 1700 500 1000 3.0 3.0 3.0 65 Ta = 55C (3, 4) Typ. Max.
Unit times times s s s s s s s s years
-- tPS --
Data retention (2)
Notes: 1. Program/erase definition This value represents the number of erasures per block. If the flash memory is programmed/erased n times, each block can be erased n times. i.e. If 4-word write is performed in 512 different addresses in the block A of 4 Kbyte and then the block is erased, it is considered the programming/erasure is performed just once. However a write in the same address more than once for one erasure is disabled. (overwrite disabled). 2. The data retention time includes the periods when the supply voltage is not applied and no clock is provided. 3. This data retention includes 3000 hours in Ta = 125C and 7000 hours in Ta = 85C. 4. Please contact a Renesas sales office regarding data retention time other than the above.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 66 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Table 5.9
E2data Flash Electrical Characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol -- -- -- tPS --
Characteristic Programming and erasure endurance of flash memory (1) Word program time Block erasure time Data retention (2) 32 Kbyte block Ta = 55C (3, 4) Flash memory circuit start-up stabilization time
Value Min. 100000 100 15 35 20 2000 200 50 Typ. Max.
Unit times s ms s years
Notes: 1. Program/erase definition This value represents the number of erasure per block. If the flash memory is programmed/erased n times, each block can be erased n times. i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it is considered the programming/erasure is performed just once. However a write in the same address more than once for one erasure is disabled. (overwrite disabled). 2. The data retention time includes the periods when the supply voltage is not applied and no clock is provided. 3. This data retention includes the following 10000 hours: 3000 hours in Ta = 125C and 7000 hours in 4. Ta = 85C. Please contact a Renesas sales office regarding data retention time other than the above.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 67 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Table 5.10
Power Supply Circuit Timing Characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol td(P-R)
Characteristic
Measurement condition
Value Min. Typ. Max. 2
Unit
Internal power supply start-up stabilization VCC = 3.0 to 5.5 V time after the main power supply is turned on
ms
t d(P-R) Internal power supply start-up stabilization time after the main power supply is turned on
V CC
Recommended operating voltage t d(P-R)
Supply voltage for internal logic PLL oscillatoroutput waveform
Figure 5.3
Power Supply Circuit Timing
Table 5.11
Electrical Characteristics of Voltage Regulator for Internal Logic (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol VVDC1
Characteristics Output voltage
Measurement condition
Value Min. Typ. 1.5 Max.
Unit V
Table 5.12
Electrical Characteristics of Low Voltage Detector (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
Vdet
Characteristics Detected voltage error
Measurement condition
Value Min. 0 Typ. Max. 0.2
Unit V V
Vdet(R)-Vdet(F) Hysteresis width Self-consuming current -- td(E-A) VCC = 5.0 V, low voltage detector enabled
4 150
A s
Operation start time of low voltage detector
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 68 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Table 5.13
Electrical Characteristics of Oscillator (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol fSO(PLL) tOSC(PLL) tjitter(p-p) f(OCO)
Characteristics PLL clock self-oscillation frequency PLL frequency synthesizer stabilization time
(1)
Measurement condition
Value Min. 35 Typ. 50 Max. 65 1 2.0 94 125 156
Unit MHz ms ns kHz
PLL jitter period (p-p) On-chip oscillator frequency
Note: 1. This value is applicable only when the main clock oscillation is stable.
Table 5.14 Electrical Characteristics of Clock Circuitry (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol trec(STOP) trec(WAIT)
Characteristics Recovery time from stop mode (1)
Measurement condition
Value Min. Typ. Max. 225 225
Unit s s
Recovery time from wait mode to low power mode
Note: 1. this recovery time does not include the period until both the main clock and sub clock oscillators are stabilized. The CPU starts operating before the oscillators are stabilized.
t rec(STOP) Recovery time from stop mode
Interrupt for exiting stop mode Main clock oscillator output On-chip oscillator output CPU clock t rec(STOP)
t rec(WAIT) Recovery time from wait mode to low power mode
Interrupt for exiting wait mode Sub clock oscillator output On-chip oscillator output CPU clock t rec(WAIT)
Figure 5.4
Clock Circuit Timing
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 69 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
Timing Requirements (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.15 Flash Memory CPU Rewrite Mode Timing
Symbol tcR tsu(S-R) th(R-S) tsu(A-R) th(R-A) tw(R) tcW tsu(S-W) th(W-S) tsu(A-W) th(W-A) tw(W) Read cycle time
Characteristics
Value Min. 200 200 0 200 0 100 200 0 30 0 30 50 Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Chip-select setup time for read Chip-select hold time after read Address setup time for read Address hold time after read Read pulse width Write cycle time Chip-select setup time for write Chip-select hold time after write Address setup time for write Address hold time after write Write pulse width
Read cycle
t su(S-R) CS0 t su(A-R) A23 to A0, BC0 to BC3
t cR t h(R-S)
t h(R-A)
t w(R) RD
Write cycle
t su(S-W) CS0 to CS3 t su(A-W) A23 to A0, BC0 to BC3
t cW t h(W-S)
t h(W-A)
t w(W) WR
Figure 5.5
Flash Memory CPU Rewrite Mode Timing
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 70 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.16 Electrical Characteristics (1) (VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 64 MHz, unless otherwise noted)
Symbol VOH
Characteristic High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to output P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
Measurement condition
Value Min. Typ. Max.
Unit
IOH = -5 mA
VCC - 2.0
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, IOH = -200 A VCC - 0.3 P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 VOL Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to output P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
VCC
V
IOL = 5 mA
2.0
V
IOL=200 A
0.45
V
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 71 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.17 Electrical Characteristics (2) (VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 64 MHz, unless otherwise noted)
Symbol VT+ - VT- Hysteresis
Characteristic
NMI, INT0 to INT5, KI0 to KI3, TA0IN to TA4IN, TA0OUT to TA4OUT, TB0IN to TB5IN, CTS0 to CTS4, CLK0 to CLK4, RXD0 to RXD4, SCL0 to SCL2, SDA0 to SDA2, SS0 to SS2, SRXD0 to SRXD2, ADTRG, IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A, UD0B, UD1A, UD1B, SCS0, SSCK0, SSI0, SSO0, LIN0IN to LIN1IN, CAN0IN, CAN0WU RESET
Measurement condition
Value Min. Typ. Max.
Unit
0.2
1.0
V
0.2
1.8
V
IIH
High level XIN, RESET, CNVSS, NSD, P0_0 to input current P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 Low level XIN, RESET, CNVSS, NSD, P0_0 to input current P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 XIN XCIN
VI = 5 V
1.0
A
IIL
VI = 0 V
-1.0
A
RPULLUP Pull-up resistor
VI = 0 V
30
50
170
k
RfXIN RfXCIN
Feedback resistor Feedback resistor
1.5 15
M M
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 72 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.18 Electrical Characteristics (3) (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
ICC
Characte ristic
Power supply current
Measurement condition
In single-chip mode, output pins are left open and others are connected to VSS XIN-XOUT Drive power: low XCIN-XCOUT Drive power: low f(CPU) = 64 MHz, f(BCLK) = 32 MHz, f(XIN) = 8 MHz, Running: PLL, Stopped: XCIN, OCO f(CPU) = fSO(PLL)/24 MHz, Running: PLL (self-oscillation), Stopped: XIN, XCIN, OCO f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Stopped: PLL, XCIN, OCO f(CPU) = f(BCLK) = 32.768 kHz, Running: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown f(CPU) = f(BCLK) = f(OCO)/4 kHz, Running: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Stopped: XCIN, PLL, OCO, Ta = 25C, Wait mode f(CPU) = f(BCLK) = 32.768 kHz, Running: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown, Ta = 25C, Wait mode f(CPU) = f(BCLK) = f(OCO)/4 kHz, Running: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown, Ta = 25C, Wait mode Stopped: all clocks, Main regulator: shutdown, Ta = 25C Stopped: all clocks, Main regulator: shutdown, Ta = 85C Stopped: all clocks, Main regulator: shutdown, Ta = 105C Stopped: all clocks, Main regulator: shutdown, Ta = 125C
Value Min. Typ. Max.
36 60
Unit
mA
7
mA
1.2
mA
220
A
230
A
960
1600
A
8
140
A
10
150
A
5
70
A
400
A
1200
A
2000
A
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 73 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.19 A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 32 MHz, unless otherwise noted)
Symbol --
Characteristic Resolution Absolute error
Measurement condition VREF = VCC VREF = VCC = 5 V AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, ANEX0, ANEX1 External op-amp connection mode
Value Min. Typ. Max. 10
Unit Bits
3
LSB
--
7
LSB
INL
Integral non-linearity error
VREF = VCC = 5 V
AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, ANEX0, ANEX1 External op-amp connection mode
3
LSB
7 1 3 3
LSB LSB LSB LSB k s s s s s
DNL -- -- tCONV
Differential non-linearity error Offset error Gain error VREF = VCC
AD = 16 MHz, with sample & hold function AD = 16 MHz, without sample & hold function
RLADDER Resistor ladder Conversion time (10 bits)
4 2.06 3.69 1.75 3.06 0.188 0
20
tCONV
Conversion time (8 bits)
AD = 16 MHz, with sample & hold function AD = 16 MHz, without sample & hold function
tSAMP VIA
AD
Sample time Analog input voltage Operating clock frequency Pull-up resistor for opencircuit detection Pull-down resistor for open-circuit detection
AD = 16 MHz
VREF 16 16 10 10 15 15
V MHz MHz k k
without sample & hold function with sample & hold function
0.125 1 5 5
RPU(AST) RPD(AST)
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 74 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.20 D/A Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol -- -- tS RO IVREF
Characteristic Resolution Absolute precision Settling time Output resistance Reference input current
Measurement condition
Value Min. Typ. Max. 8 1.0 3 4 10 20 1.5
Unit Bits % s k mA
(1)
Note: 1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for A/D converter is not considered. Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 75 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.21 External Clock Input
Symbol tc(X) tw(XH) tw(XL) tr(X) tf(X) tw / tc External clock input period
Characteristic
Value Min. 125 50 50 5 5 40 60 Max. 250
Unit ns ns ns ns ns %
External clock input high level pulse width External clock input low level pulse width External clock input rise time External clock input fall time External clock input duty
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 76 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.22 Timer A Input (Counting input in event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.23
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Timer A Input (Gating input in timer mode)
Value Min. 200 80 80 Max.
Unit ns ns ns
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.24
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Timer A Input (External trigger input in one-shot timer mode)
Value Min. 400 180 180 Max.
Unit ns ns ns
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.25
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Value Min. 200 80 80 Max.
Unit ns ns ns
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol tw(TAH) tw(TAL)
Table 5.26
Characteristic TAiIN input high level pulse width TAiIN input low level pulse width
Value Min. 80 80 Max.
Unit ns ns
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP)
Characteristic TAiOUT input clock period TAiOUT input high level pulse width TAiOUT input low level pulse width TAiOUT input setup time TAiOUT input hold time
Value Min. 2000 1000 1000 400 400 Max.
Unit ns ns ns ns ns
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 77 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.27 Timer B Input (Counting input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Table 5.28
Characteristic TBiIN input clock period (one edge counting) TBiIN input high level pulse width (one edge counting) TBiIN input low level pulse width (one edge counting) TBiIN input clock period (both edges counting) TBiIN input high level pulse width (both edges counting) TBiIN input low level pulse width (both edges counting)
Timer B Input (Pulse period measure mode)
Value Min. 200 80 80 200 80 80 Max.
Unit ns ns ns ns ns ns
Symbol tc(TB) tw(TBH) tw(TBL)
Table 5.29
Characteristic TBiIN input clock period TBiIN input high level pulse width TBiIN input low level pulse width
Timer B Input (Pulse-width measure mode)
Value Min. 400 180 180 Max.
Unit ns ns ns
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input clock period
Characteristic
Value Min. 400 180 180 Max.
Unit ns ns ns
TBiIN input high level pulse width TBiIN input low level pulse width
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 78 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Timing requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.30 Serial Interface
Symbol tc(CK) tw(CKH) tw(CKL) tsu(D-C) th(C-Q) CLKi input clock period
Characteristic
Value Min. 200 80 80 80 90 Max.
Unit ns ns ns ns ns
CLKi input high level pulse width CLKi input low level pulse width RXDi input setup time RXDi input hold time
Table 5.31
A/D Trigger Input
Symbol tw(ADH) tw(ADL)
Characteristic
ADTRG input high level pulse width Hardware trigger input high level pulse width ADTRG input low level pulse width Hardware trigger input high level pulse width
Value Min.
2----------AD
Max.
Unit ns ns
125
Table 5.32
External Interrupt INTi Input
Symbol tw(INH) tw(INL)
Characteristic
INTi input high level pulse width (1) INTi input low level pulse width (1)
Value Min. Edge sensitive Level sensitive Edge sensitive Level sensitive 250 tc(CPU) + 200 250 tc(CPU) + 200 Max.
Unit ns ns ns ns
Note: 1. The values are applied in case filtering function is disabled.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 79 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Timing requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.33 Serial Bus Interface
Symbol f(SSCK) tc(SSCK) tw(SSCKH) tw(SSCKL) tr(SSCK) tf(SSCK) th(SSCK-SCS) tsu(SSI-SSCK) th(SSCK-SSI) th(SSCK-SSO) SSCKi frequency
Characteristic
Value Min. 250 0.35 x tc(SSCK) 0.6 x tc(SSCK) 0.35 x tc(SSCK) 0.6 x tc(SSCK) 1 1 tc(BCLK) + 50 tc(BCLK) + 50 80 10 80 20 Max. 4
Unit MHz ns ns ns s s ns ns ns ns ns ns
SSCKi clock period SSCKi input high level pulse width SSCKi input low level pulse width SSCKi input rising time SSCKI input falling time SCSi input hold time SSI input setup time SSI input hold time SSO input hold time
tsu(SCS-SSCK) SCSi input setup time
tsu(SSO-SSCK) SSO input setup time
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 80 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 5 V
Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.34 Serial Interface
Symbol td(C-Q) th(C-Q)
Characteristic TXDi output delay time TXDi hold time
Measurement condition Refer to Figure 5.6
Value Min. Max. 80 0
Unit ns ns
Table 5.35
Serial Bus Interface
Symbol tw(SSCKH) tw(SSCKL) tr(SSCK) tf(SSCK)
Characteristic SSCKi output high level pulse width SSCKi output low level pulse width SSCKi output rising time SSCKi output falling time
Measurement condition
Value Min. 0.35 x tc(SSCK) 0.35 x tc(SSCK) Max. 0.6 x tc(SSCK) 0.6 x tc(SSCK) 20 20 0.5 x tc(SSCK) + 20 0.5 x tc(SSCK) - 20
Unit ns ns ns ns ns ns
td(SCS-SSCK) SSCKi output delay time for SCSi td(SSCK-SCS) SCSi output delay time for SSCKi ten(SCS-SSO) SSOi output enable time tdis(SCS-SSO) SSOi output disable time ten(SCS-SSI) SSIi output enable time tdis(SCS-SSI) SSIi output disable time td(SSCK-SSO) SSOi output delay time for SSCKi td(SSCK-SSI) SSIi output delay time for SSCKi trec(SCS) SCSi output high level period in continuous transmission Refer to Figure 5.6
1.5 x tc(BCLK) + 100 ns 1.5 x tc(BCLK) + 100 ns 1.5 x tc(BCLK) + 100 ns 1.5 x tc(BCLK) + 100 ns 30 85 0.625 x tc(SSCK) ns ns ns
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 81 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.36 Electrical Characteristics (1) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and f(CPU) = 64 MHz, unless otherwise noted)
Symbol VOH
Characteristic High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to output P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to output P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
Measurement condition
Value Min. Typ. Max.
Unit
IOH = -1 mA
VCC -0.6
VCC
V
VOL
IOL = 1 mA
0.5
V
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 82 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.37 Electrical Characteristics (2) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and f(CPU) = 64 MHz, unless otherwise noted)
Symbol
Characteristic
Measurement condition
Value Min. Typ. Max.
Unit
VT+ - VT- Hysteresis NMI, INT0 to INT5, KI0 to KI3, TA0IN to TA4IN, TA0OUT to TA4OUT, TB0IN to TB5IN, CTS0 to CTS4, CLK0 to CLK4, RXD0 to RXD4, SCL0 to SCL2, SDA0 to SDA2, SS0 to SS2, SRXD0 to SRXD2, ADTRG, IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A, UD0B, UD1A, UD1B, SCS0, SSCK0, SSI0, SSO0, LIN0IN to LIN1IN, CAN0IN, CAN0WU
RESET
0.2
1.0
V
0.2
1.8
V
IIH
High level XIN, RESET, CNVSS, NSD, P0_0 to input P0_7, P1_0 to P1_7, P2_0 to P2_7, current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 Low level XIN, RESET, CNVSS, NSD, P0_0 to input P0_7, P1_0 to P1_7, P2_0 to P2_7, current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7
VI = 3 V
1.0
A
IIL
VI= 0 V
-1.0
A
RPULLUP Pull-up resistor
VI = 0 V
50
100
500
k
RfXIN RfXCIN
Feedback XIN resistor Feedback XCIN resistor
3 25
M M
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 83 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.38 Electrical Characteristics (3) (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
ICC
Characte ristic
Power supply current In single-chip mode, output pins are left open and others are connected to VSS XIN-XOUT Drive power: low XCIN-XCOUT Drive power: low
Measurement condition
f(CPU) = 64 MHz, f(BCLK) = 32 MHz, f(XIN) = 8 MHz, Running: PLL, Stopped: XCIN, OCO f(CPU) = fSO(PLL)/24 MHz, Running: PLL (self-oscillation), Stopped: XIN, XCIN, OCO f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Stopped: PLL, XCIN, OCO f(CPU) = f(BCLK) = 32.768 kHz, Running: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown f(CPU) = f(BCLK) = f(OCO)/4 kHz, Running: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Stopped: PLL, XCIN, OCO, Ta = 25C, Wait mode f(CPU) = f(BCLK) = 32.768 kHz, Running: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown, Ta = 25C, Wait mode f(CPU) = f(BCLK) = f(OCO)/4 kHz, Running: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown, Ta = 25C, Wait mode Stopped: all clocks, Main regulator: shutdown, Ta = 25C Stopped: all clocks, Main regulator: shutdown, Ta = 85C Stopped: all clocks, Main regulator: shutdown, Ta = 105C Stopped: all clocks, Main regulator: shutdown, Ta = 125C
Value Min. Typ. Max.
36 60
Unit
mA
7
mA
670
A
180
A
190
A
500
900
A
8
140
A
10
150
A
5
70
A
400
A
1200
A
2000
A
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 84 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.39 A/D Conversion Characteristics (VCC= AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 32 MHz, unless otherwise noted)
Symbol --
Characteristic Resolution Absolute error
Measurement condition VREF = VCC VREF = VCC = 3.3 V AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, ANEX0, ANEX1 External op-amp connection mode
Value Min. Typ. Max. 10
Unit Bits
5
LSB
--
7
LSB
INL
Integral non-linearity error
VREF = VCC = 3.3 V
AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, ANEX0, ANEX1 External op-amp connection mode
5
LSB
7 1 3 3
LSB LSB LSB LSB k s s s
DNL -- -- tCONV tCONV tSAMP VIA
AD
Differential non-linearity VREF = VCC = 3.3 V Offset error Gain error VREF = VCC
AD = 10 MHz, with sample & hold function AD = 10 MHz, with sample & hold function AD = 10 MHz
RLADDER Resistor ladder Conversion time (10 bits) Conversion time (8 bits) Sampling time Analog input voltage Operating clock frequency
4 3.3 2.8 0.3 0
20
VREF 10 10 10 10 15 15
V MHz MHz k k
without sample & hold function with sample & hold function
0.125 1 5 5
RPU(AST) Pull-up resistor for open-circuit detection RPD(AST) Pull-down resistor for open-circuit detection
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 85 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.40 D/A Conversion Characteristics (VCC= AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol -- -- tS RO IVREF
Characteristic Resolution Absolute precision Settling time Output resistance Reference input current
Measurement condition Min.
Value Typ. Max. 8 1.0 3 4 10 20 1.0
Unit Bits % s k mA
(1)
Note: 1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for A/D converter is not considered. Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 86 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.41 External Clock Input
Symbol tc(X) tw(H) tw(L) tr tf tw / tc
Characteristic External clock input period External clock input high level pulse width External clock input low level pulse width External clock input rise time External clock input fall time External clock input duty
Value Min. 125 50 50 5 5 40 60 Max. 250
Unit ns ns ns ns ns %
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 87 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.42 Timer A Input (Counting input in event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.43
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Timer A Input (Gating input in timer mode)
Value Min. 200 80 80 Max.
Unit ns ns ns
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.44
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Timer A Input (External trigger input in one-shot timer mode)
Value Min. 400 180 180 Max.
Unit ns ns ns
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.45
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Value Min. 200 80 80 Max.
Unit ns ns ns
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol tw(TAH) tw(TAL)
Table 5.46
Characteristic TAiIN input high level pulse width TAiIN input low level pulse width
Value Min. 80 80 Max.
Unit ns ns
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP)
Characteristic TAiOUT input clock period TAiOUT input high level pulse width TAiOUT input low level pulse width TAiOUT input setup time TAiOUT input hold time
Value Min. 2000 1000 1000 400 400 Max.
Unit ns ns ns ns ns
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 88 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.47 Timer B Input (Counting input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Table 5.48
Characteristic TBiIN input clock period (one edge counting) TBiIN input high level pulse width (one edge counting) TBiIN input low level pulse width (one edge counting) TBiIN input clock period (both edges counting) TBiIN input high level pulse width (both edges counting) TBiIN input low level pulse width (both edges counting)
Timer B Input (Pulse period measure mode)
Value Min. 200 80 80 200 80 80 Max.
Unit ns ns ns ns ns ns
Symbol tc(TB) tw(TBH) tw(TBL)
Table 5.49
Characteristic TBiIN input clock period TBiIN input high level pulse width TBiIN input low level pulse width
Timer B Input (Pulse-width measure mode)
Value Min. 400 180 180 Max.
Unit ns ns ns
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input clock period
Characteristic
Value Min. 400 180 180 Max.
Unit ns ns ns
TBiIN input high level pulse width TBiIN input low level pulse width
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 89 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.50 Serial Interface
Symbol tc(CK) tw(CKH) tw(CKL) tsu(D-C) th(C-D) CLKi input clock period
Characteristic
Value Min. 200 80 80 80 90 Max.
Unit ns ns ns ns ns
CLKi input high level pulse width CLKi input low level pulse width RXDi input setup time RXDi input hold time
Table 5.51
A/D Trigger Input
Symbol tw(ADH) tw(ADL)
Characteristic
ADTRG input high level pulse width Hardware trigger input high pulse width ADTRG input low level pulse width Hardware trigger input high pulse width
Value Min.
2----------AD
Max.
Unit ns ns
125
Table 5.52
External Interrupt INTi Input
Symbol tw(INH) tw(INL)
Characteristic
INTi input high level pulse width (1) INTi input low level pulse width (1)
Value Min. Edge sensitive Level sensitive Edge sensitive Level sensitive 250 tc(CPU) + 200 250 tc(CPU) + 200 Max.
Unit ns ns ns ns
Note: 1. The values are applied in case filtering function is disabled.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 90 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.53 Serial Bus Interface
Symbol f(SSCK) tc(SSCK) tw(SSCKH) tw(SSCKL) tr(SSCK) tf(SSCK) th(SSCK-SCS) tsu(SSI-SSCK) th(SSCK-SSI) th(SSCK-SSO) SSCKi frequency
Characteristic
Value Min. 250 0.35 x tc(SSCK) 0.6 x tc(SSCK) 0.35 x tc(SSCK) 0.6 x tc(SSCK) 1 1 tc(BCLK) + 50 tc(BCLK) + 50 100 10 100 20 Max. 4
Unit MHz ns ns ns s s ns ns ns ns ns ns
SSCKi clock period SSCKi input high level pulse width SSCKi input low level pulse width SSCKi input rising time SSCKI input falling time SCSi input hold time SSI input setup time SSI input hold time SSO input hold time
tsu(SCS-SSCK) SCSi input setup time
tsu(SSO-SSCK) SSO input setup time
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 91 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
VCC = 3.3 V
Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.54 Serial Interface
Symbol td(C-Q) th(C-Q)
Characteristic TXDi output delay time TXDi hold time
Measurement condition Refer to Figure 5.6
Value Min. Max. 80 0
Unit ns ns
Table 5.55
Serial Bus Interface
Symbol tw(SSCKH) tw(SSCKL) tr(SSCK) tf(SSCK)
Characteristic SSCKi output high level pulse width SSCKi output low level pulse width SSCKi output rising time SSCKi output falling time
Measurement condition
Value Min. 0.35 x tc(SSCK) 0.35 x tc(SSCK) Max. 0.6 x tc(SSCK) 0.6 x tc(SSCK) 35 35 0.5 x tc(SSCK) + 40 0.5 x tc(SSCK) - 40
Unit ns ns ns ns ns ns
td(SCS-SSCK) SSCKi output delay time for SCSi td(SSCK-SCS) SCSi output delay time for SSCKi ten(SCS-SSO) SSOi output enable time tdis(SCS-SSO) SSOi output disable time ten(SCS-SSI) SSIi output enable time tdis(SCS-SSI) SSIi output disable time td(SSCK-SSO) SSOi output delay time for SSCKi td(SSCK-SSI) SSIi output delay time for SSCKi trec(SCS) SCSi output high level period in continuous transmission Refer to Figure 5.6
1.5 x tc(BCLK) + 100 ns 1.5 x tc(BCLK) + 100 ns 1.5 x tc(BCLK) + 100 ns 1.5 x tc(BCLK) + 100 ns 50 120 0.625 x tc(SSCK) ns ns ns
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 92 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
MCU
Pin to be measured
30 pF
Figure 5.6
Switching Characteristic Measurement Circuit
t c(X)
XIN
t w(XH) t r(X) t f(X) t w(XL)
Figure 5.7
External Clock Input Timing
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 93 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
t c(TA) t w(TAH) TAiIN input t c(UP) t w(UPH) TAiOUT input t w(UPL) t w(TAL)
In event counter mode TAiOUT input (input for increment/ decrement count switching) t su(UP-TIN) TAiIN input (in falling edge counting) t h(TIN-UP)
TAiIN input (in rising edge counting) t c(TB) t w(TBH) TBiIN input t c(CK) t w(CKH) CLKi t d(C-Q) TXDi t su(D-C) RXDi t h(C-D) t h(C-Q) t w(CKL) t w(TBL)
t w(ADL) ADTRG input
t w(ADH)
t w(INL) INTi input 2 CPU clock cycles + 300 ns or more NMI input
t w(INH)
2 CPU clock cycles + 300 ns or more
Figure 5.8
Timing of Peripheral Functions
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 94 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
5. Electrical Characteristics
t c(SSCK) SSCKi t w(SSCKH) t r(SSCK) SCSi (output) SSCKi (output) CPOS = 1 CPOS = 0 t en(SCS-SSO) SSOi (output) t dis(SCS-SSO) t d(SCS-SSCK) t d(SSCK-SCS) t f(SSCK) t w(SSCKL)
t rec(SCS)
SCSi (input) SSCKi (input) CPOS = 1 CPOS = 0 t en(SCS-SSI) SSIi (output) t dis(SCS-SSI) t su(SCS-SSCK) t h(SSCK-SCS)
SSCKi CPOS = 1 CPOS = 0 SSIi / SSOi (output) CPHS = 1 t d(SSCK-SSI) t d(SSCK-SSO) CPHS = 0 SSIi / SSOi (input) CPHS = 1 t su(SSI-SSCK) t su(SSO-SSCK) CPHS = 0 t h(SSCK-SSI) t h(SSCK-SSO) t su(SSI-SSCK) t su(SSO-SSCK) t h(SSCK-SSI) t h(SSCK-SSO) t d(SSCK-SSI) t d(SSCK-SSO)
Figure 5.9
Timing of Serial Bus Interface
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 95 of 96
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/120 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g
HD *1 D
75
51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
76
50
bp b1 HE E
Reference Dimension in Millimeters Symbol
*2
c1
c
Terminal cross section
1 Index mark ZD
25 F
ZE
100
26
A2
A
D E A2 HD HE A A1 bp b1 c c1
c
A1
y e
*3
bp
L L1 Detail F
x
e x y ZD ZE L L1
Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0
REJ03B0236-0050 Rev.0.50 Jul 31, 2008 Page 96 of 96
REVISION HISTORY
Rev. 0.31 0.50 Date Feb 14, 2008 Jul 31, 2008 Page -- -- 1 6 11-13 11
R32C/120 Group Datasheet
Description Summary Initial release Second edition released Chapter 1 * "(MCUs)" in line 1 of 1.1 added * "This specification" in "Notes to users" changed to "Specifications" * Figure 1.2 modified * "Functional Category" and "Function" in Tables 1.7 to 1.9 changed to "Function" and "Description", respectively * Expression "internal logic voltage regulator" for "Connecting pins for decoupling capacitor" in Table 1.7 changed to "internal voltage" * Descriptions for "I/O ports" and "Input port" in Table 1.7 modified Chapter 2 * "Interrupt table register" in Figure 2.1 and 2.1.6 changed to "Interrupt vector table base register" * Descriptions for 2.1 revised Chapter 3 * Descriptions for Chapter 3 modified Chapter 4 * Some "SFR"s pluralized * Description for initial paragraph of Chapter 4 modified * "DMAi interrupt" in Tables 4.2 and 4.3 changed to "DMAi transfer complete interrupt" * Reset value for PLS in Table 4.18 changed * "DMAi Source Select Register j" in Table 4.24 changed to "DMAi Request Source Select Register j" * Addresses "047F60h to 047FFFh" and "048000h to 04FFFFh" added to Table 4.41 Chapter 5 * This chapter newly added
14, 15 15, 16 18 -- 19 20, 21 36 42 59
60-95
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